Method of generating test patterns for a logic circuit, a system performing the method, and a computer readable medium instructing the system to perform the method
AssigneeNEC Corporation
InventorsToshinobu Ono, Tamaki Toumiya
Life of this patent
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Abstract
In a method of test pattern generation for logic circuits, a whole circuit is divided into a plurality of partial circuits for test pattern generation by distributed-processing. ATG (Algorithmic Test Generation) process is performed per each of the partial circuits based on the result of RTG (Random Test Generation) process. Also disclosed are a test pattern generation system performing the method, and computer readable media having program for the test pattern generation system to perform the method.
Claims27
A method of generating test patterns for a logic circuit, comprising the steps of:
- (a) generating a random test pattern for detecting at least one fault in a logic circuit;
- (b) extracting a plurality of partial circuits from said logic circuit;
- and
- (c) generating an algorithmic test pattern for each of said plurality of partial circuits for detecting faults other than said at least one fault detected in step (a).
A system for generating logic circuit test patterns, comprising:
- random test pattern generating means for generating a random test pattern, and for executing fault simulation to detect at least one fault of a logic circuit based on said random test pattern;
- partial circuit creating means for extracting a plurality of partial circuits from said logic circuit;
- algorithmic test pattern generating means for generating a test pattern for each of said plurality of partial circuits for detecting faults other than said fault detected by said random test pattern;
- and
- pattern merging means for merging test patterns generated by said random test pattern generating means and argorithmic test pattern generating means.
A computer readable medium having a test pattern generation program recorded thereon for performing the following steps when such program is executed on a test pattern generation system:
- (a) generating random test patterns for detecting at least one fault of a logic circuit;
- (b) extracting a plurality of partial circuits from said logic circuit;
- (c) generating an algorithmic test pattern for each of said plurality of partial circuits for detecting faults other than said fault detected in step (a);
- and
- (d) merging test patterns generated in step (a) and generated in step (c), and outputting a merged pattern as a test pattern of said logic circuit.
Dependencies are inferred from the claim text.