Multi-function timer with shared hardware

A multi-function timer comprising:

• a plurality of slots, each of said slots including a control register, status register and a plurality of data registers, each slot representing an independent process;
• a slot pointer for identifying a current slot and associated plurality of instructions representing a process, said slot pointer configured to repeatedly sequence through each of said slots;
• a logic controller in operative communication with said slots, said logic controller for reading instructions from said control registers and writing instructions to said status registers;
• and
• a processor for performing functions of said instructions, said processor in operative communication with said logic controller and said data registers of said slots,
• wherein each of said slots is configured to perform a process selected from the group consisting of:
• pulse width modulation (PWM), high speed input (HSI), high speed output (HSO), or delta time input (DTI).

In a multi-function timer comprising a plurality of slots, each of said slots including a control register, status register and a plurality of data registers and wherein each slot represents a timing process selected from the group consisting of:

• pulse width modulation (PWM), high speed input (HSI), high speed output (HSO) and delta time input (DTI), a method of processing timed events comprising the steps of:
• identifying one of the slots as the current slot with a slot pointer;
• reading said control register to identify the timing process associated with said current slot;
• identifying one set of instructions as a current set of instructions associated with said selected timing process;
• performing functions of the current instruction set associated with said selected timing process;
• and
• indexing said slot pointer to identify the next slot in sequence as the current slot.