Processor and method of fetching an instruction that select one of a plurality of decoded fetch addresses generated in parallel to form a memory request

A processor, comprising.

• means for determining a plurality of decoded target addresses from a plurality of previously fetched instructions and for determining a decoded sequential address from a last of said plurality of previously fetched instructions;
• means for generating a select signal specifying one of said plurality of decoded target addresses or said decoded sequential address, wherein said means for generating generates the select signal concurrently with said determination of said plurality of decoded target addresses and said decoded sequential address to accelerate memory access;
• means for selecting one of said plurality of decoded target addresses or said decoded sequential address as a decoded memory request address utilizing is said select signal;
• means for transmitting said decoded memory request address from said processor to a memory so that said memory will supply at least one instruction to said processor;
• and
• means for executing instructions.

A processor having an associated memory, said processor comprising:

• an execution unit that executes dispatched instructions;
• an instruction queue that can contain a plurality of instructions to be dispatched;
• address determination circuitry that determines a plurality of decoded target addresses and a decoded sequential address from a plurality of previously fetched instructions contained within said instruction queue, said address determination circuitry including a plurality of address decoders;
• and
• priority logic that selects one of said plurality of decoded target addresses or said decoded sequential address as a decoded memory request address, wherein said priority logic determines which of said plurality of decoded target address to select concurrently with said determination of said plurality of decoded-target addresses and-said decoded sequential address by said address determination circuitry to accelerate access to the associated memory.