Back to results
US 6,334,179 B1Granted
DSP coprocessor having control flags mapped to a dual port section of memory for communicating with the host
AssigneeMasaana Research Limited
InventorsPhilip Curran, Brian Murray, Paul Costigan, Mark Dunn
Life of this patent
Estimating the term…
Abstract
A DSP coprocessor 2 is connected to a host sub-system (3). The host sub-system (3) has a host processor (4), a host RAM (5), and shared RAM banks (6, 7). Multiplexers (11) provide access for either the DSP or the host to a shared RAM bank. Macro commands for functions of the DSP coprocessor are retrieved from the shared RAM banks. This allows comprehensive interaction of the host and the DSP coprocessor.
Claims18
A DSP coprocessor comprising:
- an arithmetic logic unit;
- an address generation unit;
- a program control unit;
- a memory for storing a library of functions, each said function having a set of instructions;
- means for accessing a shared random access memory to which a host processor also has access;
- means for reading from said shared random access memory a macro command to activate a stored function selected by the host processor;
- means in the program control unit for executing said function without intervention from the host processor, and for writing results of execution of said function to the shared random access memory;
- and
- wherein the shared random access memory includes a dual port section and busy and bus request flags are mapped to said dual port section, whereby a host may read or write a flag without affecting coprocessor operations.
6 more elements
A DSP coprocessor system comprising:
- a DSP coprocessor;
- an arithmetic logic unit;
- an address generation unit;
- a program control unit;
- a memory for storing a library of functions, each said function having a set of instructions;
- means for accessing a shared random access memory to which a host processor also has access;
- means for reading from said shared random access memory a macro command to activate a stored function selected by the host processor;
- means in the program control unit for executing said function without intervention from the host processor, and for writing results of execution of said function to the shared random access memory, and said shared random access memory having means for allowing host processor access;
- and
- wherein the shared random access memory includes a dual port section and busy and bus request flags are mapped to said dual port section, whereby a host may read or write a flag without affecting coprocessor operations.
7 more elements
A DSP coprocessor comprising:
- an arithmetic logic unit;
- an address generation unit;
- a program control unit including a read only memory storing a library of functions, each said function having a set of instructions;
- means in said units for addressing a shared random access memory which is external to the coprocessor and which is shared with a host processor, said addressing means including
- means for reading instructions for a programmable function from a mapped instruction section of said shared random access memory,
- means for reading initialization instructions from a parameter mapped section of said shared random access memory,
- means for reading a macro command from said parameter mapped section, and for using said macro command to identify a function in either the program control unit read only memory or in the instruction section of said shared random access memory,
- means in the program control unit for executing the identified function without intervention from the host processor and for writing results of execution of said function to said shared random access memory, and
- wherein the shared random access memory includes a dual port section and busy and bus request flags are mapped to said dual port section, whereby a host may read or write a flag without affecting coprocessor operations.
6 more elements
Dependencies are inferred from the claim text.