Switchable memory system and memory allocation method

A memory allocator comprising:

• a first multiport digital processing unit (DSP) having multiple address and data buses coupled to access a corresponding different type of memory space wherein each of the different types of memory space includes a plurality of memory banks;
• a second multiport digital processing unit having multiple address and data buses coupled to access the corresponding different type of memory space;
• and
• a controllable switching circuit, operatively coupled to the multiple address and data buses and to each of the different types of memory space, and operatively responsive to memory type data indicating whether the different memory space is for storing program code, left data or right data and configured to provide programmable memory allocation of the different types of memory space for a non-corresponding set of address and data buses and to provide concurrent access to more than one set of address and data buses to each of the different types of memory spaces for each of the first and second DSPs wherein the controllable switching circuit includes:
• a plurality of switching circuits each operatively coupled to a corresponding memory bank;
• and
• at least one bank selecting circuit coupled to each of the plurality of switching circuits that select banks of memory based on memory allocation requirement data corresponding to each of the DSPs.

A method of allocating memory comprising the steps of:

• determining memory allocation requirement data for different types of memory space based on at least data representing an amount of program memory usage and data representing an amount of program memory usage and data representing an amount of data memory usage;
• determining for each type of memory space, based on the memory requirement data, whether additional memory space is required;
• providing memory type identification (ID) data that indicates which of the set of address buses to select;
• and
• allocating the different types of memory space for a non-corresponding set of address and data buses and providing concurrent access to more than one set of address and data buses to each of the different types of memory spaces.