US 6,334,174 B1 · Dynamically-tunable memory controller

Abstract

A memory controller circuit arrangement and method utilize a tuning circuit that dynamically controls the timing of memory control operations, rather than simply relying on fixed timing parameters that are either hardwired or initialized upon startup of a memory controller. Dynamic control over the timing of memory control operations typically incorporates memory test control logic that verifies whether or not a memory storage device will reliably operate using the dynamically-selected values of given timing parameters. Then, based upon the results of such testing, such dynamically-selected values are selectively updated and retested until optimum values are found. The dynamically-selected values may be used to set one or more programmable registers, each of which may in turn be used to control the operation of a programmable delay counter that enables a state transition in a state machine logic circuit to initiate performance of a memory control operation by the logic circuit. Dynamic tuning may also utilize a unique binary search engine circuit arrangement that updates one of two registers with an average of the current values stored in such registers based upon the result of a test performed using that average value. By selectively updating such registers, a fast convergence to an optimum value occurs with minimal circuitry.

Claims22

Dependent claims

A memory controller circuit arrangement, comprising:

(a) a logic circuit configured to control data transfer with at least one memory storage device by performing first and second memory control operations;
and
(b) a tuning circuit coupled to the logic circuit and configured to dynamically control the delay between the first and second memory control operations by generating a delay count representing a number of clock cycles to delay performance of the second memory control operation relative to the first memory control operation, wherein the tuning circuit includes parameter manipulation control logic configured to select a test value among a plurality of values for the delay count, the parameter manipulation control logic including a binary search engine.

A memory controller circuit arrangement, comprising:

(a) a logic circuit configured to control data transfer with at least one memory storage device by performing first and second memory control operations;
(b) a tuning circuit coupled to the logic circuit and configured to dynamically control the delay between the first and second memory control operations, wherein the tuning circuit includes parameter manipulation control logic configured to select a test value among a plurality of values for the delay between the first and second memory control operations;
and
(c) memory test control logic configured to perform at least one memory test on the memory storage device while the delay between the first and second memory control operations is set to the test value by the parameter manipulation control logic;
wherein the parameter manipulation control logic includes a binary search engine, the binary search engine including first and second registers respectively configured to store first and second values;
and an averaging circuit coupled to receive the first and second values stored in the first and second registers, and to output as the test value an average of the first and second values, wherein the first register is configured to be updated with the test value responsive to a successful memory test performed by the memory test control logic using the test value, and wherein the second register is configured to be updated with the test value responsive to an unsuccessful memory test performed by the memory test control logic using the test value, and wherein the first and second registers are further configured to be respectively initialized to upper and lower limit values, wherein the binary search engine further includes a subtraction circuit configured to output a complete signal responsive to the value stored in the first register being one greater than the value stored in the second register;
whereby upon outputting of the complete signal an optimum value for the delay between the first and second memory control operations is stored in the first register.

4 more elements

Dependencies are inferred from the claim text.

Dynamically-tunable memory controller

Life of this patent

Dynamically-tunable memory controller

Life of this patent

Abstract

Claims22