Combined cache with main memory and a control method thereof

A cache memory system including a full associative mapping structure comprising;

• a first selection means for selectively outputting one out of an address on a address bus when a data is loaded into the cache memory system from a main memory and an address of a first mapping region in which the cache memory system is mapped into the main memory in response to a cache/memory signal;
• a first tag register for storing an address from the first selection means;
• a first comparison means for comparing the address stored in the first tag register with the address inputted from the address bus to read out data from the cache memory system;
• a second selection means for selectively outputting one out of an address on an address bus when a data is loaded into the cache memory system from the main memory and an address of a second mapping region in which the cache memory system is mapped into the main memory in response to the cache/memory signal;
• a second tag register for storing an address from the second selection means;
• a second comparison means for comparing the address stored in the second tag register with the address inputted from the address bus to read out data from the cache memory system;
• a first logic operation means for performing a logic OR operation with outputs from the first and second comparison means;
• a tag hit latch circuit for storing a tag hit signal produced by an output signal from the logic operation means;
• first and second data registers for storing data which are loaded into the cache memory system from the main memory, respectively;
• a third selection means for selectively outputting data stored in the first and second registers in response to the outputs from the first and second comparison means;
• first and second valid bit registers for storing valid bits indicative of a validity of data stored in the first and second data registers;
• a fourth selection means for selectively outputting the valid bits stored in the first and second valid bit registers in response to the outputs from the first and second comparison means;
• and
• a second logic operation means for performing a logic AND operation with the tag hit signal for the tag hit latch circuit and the valid bit from the fourth selection means.

A cache memory system including a directly mapped structure comprising:

• a first selection means for selectively outputting one out of a tag field on a address bus when a data is loaded into the cache memory system from a main memory and an address value corresponding to a starting address point of a mapping region in which the cache memory system is mapped into the main memory in response to a cache/memory signal;
• a tag register for storing a tag value from the first selection means;
• a comparison means for comparing the tag value stored in the tag register with the tag field inputted from the address bus to read out data from the cache memory system;
• a tag hit latch circuit for storing an output signal from the comparison means as a tag hit signal;
• a plurality data registers for storing data which are loaded into the cache memory system from the main memory;
• a second selection means for selectively outputting the data stored in the plurality of data registers in response to an offset field on the address bus which is provided for reading out data from the cache memory system;
• a plurality of valid bit registers for storing valid bits indicative of a validity of data stored in the plurality of data registers;
• a third selection means for selectively outputting the valid bits of data stored in the plurality of valid bit registers in response to the offset field;
• and
• a logic operation means for performing a logic AND operation with the tag hit signal outputted from the tag hit latch circuit and the valid bits form the third selection means.

A method for controlling a cache memory system which uses an internal cache of a microprocessor as a main memory, the method comprising the steps of:

• ascertaining a logic value of an arbitrary cache/memory bit indicative of the internal cache execution of the microprocessor from a plurality of bits stored in a system control register which controls hardware associated with the microprocessor;
• ascertaining whether an address, which is inputted to read out a data, exists in a mapping region of an internal cache memory in a mapping region if the logic value indicates that the internal cache is used the main memory;
• and
• reading out the data from the main memory if there is not the address in the mapping region and reading out the data from the cache memory if there is the address in the mapping region.