Cache coherency protocol with tagged state for modified values

A computer system comprising:

• a system memory device;
• a bus connected to said system memory device;
• a plurality of processing units connected to said bus, each of said processing units having at least one cache line for storing values from said system memory device;
• and
• cache coherency means for sourcing a modified value from a first cache line of a first processing unit to a second cache line of a second processing unit, the modified value corresponding to a memory block of said system memory device, and for assigning a tagged coherency state to only a selected one of the first and second cache lines indicating that the selected cache line contains the modified value and that the modified value has not been written to said memory block of said system memory device.

A computer system comprising:

• a system memory device;
• a bus connected to said system memory device;
• a plurality of processing units connected to said bus, each of said processing units having at least one cache line for storing values from said system memory device;
• and
• cache coherency means for (i) sourcing a modified value from a first cache line of a first one of said processing units to a second cache line of a second one of said processing units, the modified value being associated with a memory block of said system memory device, (ii) assigning a first coherency state to said first cache line to indicate that said first cache line contains a shared copy of the modified value which has been most recently accessed, and that the modified value has been written to a lower level location in a memory hierarchy of the computer system, and (iii) assigning a second coherency state to said second cache line to indicate that said second cache line contains the modified value and will exclusively source the modified value, and that the modified value has not been written to said memory block of said system memory device.

A computer system comprising:

• a system memory device;
• a bus connected to said system memory device;
• a first plurality of processing units each having a cache for storing values from said system memory device, said first plurality of processing units being grouped into a first processing unit cluster;
• a second plurality of processing units each having a cache for storing values from said system memory device, said second plurality of processing units being grouped into a second processing unit cluster;
• a first cache cluster connected to each of said first plurality of processing units, and to said bus;
• a second cache cluster connected to each of said second plurality of processing units, and to said bus;
• and
• is cache coherency means for assigning a tagged coherency state to a first cache line of a cache associated with a first processing unit in the first processing unit cluster, to indicate that the first cache line contains a modified value corresponding to a memory block of said system memory device and that the modified value has not been written to said memory block of said system memory device, and for assigning the tagged coherency state to a second cache line of a cache associated with a second processing unit in the second processing unit cluster, to indicate that the second cache line contains the modifies value and that the modified value has not been written to said memory block of said system memory device.