Write-combining device for uncacheable stores

A computer system, comprising:

• a processor;
• a memory device coupled to the processor via a bus;
• a write-combining device coupled to each of the processor and the memory device via the bus, the write-combining device including:
• a memory order buffer to receive first and second stores;
• and
• a data cache address and control coupled to the memory order buffer and having at least one storage buffer, the data address and control to receive the first and second stores from the memory order buffer, the first and second stores being write-combined if the first and second stores are sequentially-executed from a same thread.

A method for write-combining uncacheable stores, the method comprising:

• receiving first and second stores at a memory order buffer;
• determining whether the first and second scores are sequentially-executed within a same thread;
• and
• write-combining the first and second stores in a storage buffer if the first and second stores are determined to be sequentially-executed within the same thread.