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US 6,334,166 B1Granted
Processor system using synchronous dynamic memory
AssigneeHitachi, Ltd.
InventorsKunio Uchiyama, Osamu Nishii
Life of this patent
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Abstract
A main storage apparatus is a synchronous dynamic memory having a plurality of memory banks and a mode register for determining an operation mode, a main storage controller is coupled to a processor and the main storage apparatus, and means to realize controlling of parallel access to a plurality of banks of the memory and controlling of setting of an operation mode to the built-in register is arranged in the main storage controller. Accordingly, the use of a conventional processor of high generality and a conventional memory can be ensured.
Claims37
A processor system comprising:
- a memory having a mode register for identifying an operation mode, wherein said memory operates in synchronism with a first clock signal generated externally from said memory, said memory formed on a single chip;
- and
- a data processor formed on a single chip, wherein said data processor operates in synchronism with a second clock signal,
- wherein said data processor includes:
- a microprocessor;
- and
- a control unit coupled to said microprocessor and said memory;
- wherein said control unit transfers command information to input terminals of said memory;
- wherein said first clock signal is in synchronism with said second clock signal.
6 more elements
A processor system comprising:
- a memory having a plurality of memory banks and a mode register for identifying an operation mode, wherein said memory operates in synchronism with a clock signal generated externally from said memory;
- a microprocessor providing operation mode information to be stored in said mode register of said memory;
- and
- a control unit coupled to said microprocessor and said memory, said control unit transferring said operation mode information to said mode register of said memory and operates in synchronism with said clock signal;
- wherein said microprocessor and said control unit are provided as mutually separate individual chip areas on a same semiconductor chip.
2 more elements
A processor system comprising:
- a memory having a mode register for identifying an operation mode, wherein said memory operates in synchronism with a clock signal generated externally from said memory, wherein said memory is formed on a single chip;
- a microprocessor providing operation mode information to be stored in said mode register of said memory;
- and
- a control unit coupled to said microprocessor and said memory, said control unit transferring said operation mode information to said mode register of said memory and operates in synchronism with said clock signal;
- wherein said microprocessor and said control unit are provided as mutually separate individual chip areas on a same semiconductor chip.
2 more elements
A processor system comprising:
- a memory having a mode register for identifying an operation mode wherein said memory operates in synchronism with a clock signal generated externally from said memory;
- a microprocessor providing operation mode information to be stored in said mode register of said memory;
- and
- a control unit coupled to said microprocessor and said memory, said control unit transferring said operation mode information to said mode register of said memory and operates in synchronism with said clock signal;
- wherein said microprocessor and said control unit are provided as mutually separate individual chip areas on a same semiconductor chip.
2 more elements
A processor system comprising:
- a memory having a mode register for identifying an operation mode, wherein said memory operates in synchronism with a first clock signal generated externally from said memory, said memory formed on a single chip;
- and
- a data processor operating in synchronism with a second clock signal,
- wherein said data processor includes:
- a microprocessor formed on a second chip;
- and
- a control unit formed on a third chip and coupled to said microprocessor and said memory;
- wherein said control unit transfers command information to input terminals of said memory;
- wherein said first clock signal is in synchronism with said second clock signal.
6 more elements
A processor system comprising:
- a memory having a plurality of memory banks and a mode register for identifying an operation mode, wherein said memory operates in synchronism with a clock signal generated externally from said memory;
- a microprocessor providing operation mode information to be stored in said mode register of said memory;
- and
- a control unit coupled to said microprocessor and said memory, said control unit transferring said operation mode information to said mode register of said memory and operates in synchronism with said clock signal;
- wherein said memory, said microprocessor and said control unit are provided as mutually separate individual semiconductor chips.
2 more elements
A processor system comprising:
- a memory having a mode register for identifying an operation mode wherein said memory operates in synchronism with a clock signal generated externally from said memory;
- a microprocessor providing operation mode information to be stored in said mode register of said memory;
- and
- a control unit coupled to said microprocessor and said memory, said control unit transferring said operation mode information to said mode register of said memory and operates in synchronism with said clock signal;
- wherein said memory, said microprocessor and said control unit are provided as mutually separate individual semiconductor chips.
2 more elements
A processor system comprising:
- a memory having a mode register for identifying an operation mode wherein said memory operates in synchronism with a clock signal generated externally from said memory;
- a microprocessor providing operation mode information to be stored in said mode register of said memory;
- and
- a control unit coupled to said microprocessor and said memory, said control unit transferring said operation mode information to said mode register of said memory and operates in synchronism with said clock signal;
- wherein said memory is provided as a plurality of first semiconductor chips, said microprocessor is provided as a second semiconductor chip, and said control unit is provided as a third semiconductor chip.
2 more elements
A processor system comprising:
- a memory having a mode register for identifying an operation mode, wherein said memory operates in synchronism with a clock signal generated externally from said memory;
- and
- a data processor,
- wherein said data processor includes:
- a microprocessor;
- and
- a control unit coupled to said microprocessor and said memory;
- wherein said control unit transfers command information to input terminals of said memory and operates in synchronism with said clock signal;
- and
- wherein at least said microprocessor and said controller are formed as separate chip areas on a single semiconductor chip.
7 more elements
A processor system comprising:
- a memory having a mode register for identifying an operation mode wherein said memory operates in synchronism with a clock signal generated externally from said memory;
- a microprocessor providing operation mode information to be stored in said mode register of said memory;
- and
- a control unit coupled to said microprocessor and said memory, said control unit transferring said operation mode information to said mode register of said memory and operates in synchronism with said clock signal;
- wherein at least said microprocessor and said control unit are provided as mutually separate individual chip areas on a same semiconductor chip.
2 more elements
A processor system comprising:
- a memory having a mode register for identifying an operation mode wherein said memory operates in synchronism with a clock signal generated externally from said memory, wherein said memory is formed on a single chip;
- a microprocessor providing operation mode information to be stored in said mode register of said memory;
- and
- a control unit coupled to said microprocessor and said memory, said control unit transferring said operation mode information to said mode register of said memory and operates in synchronism with said clock signal;
- wherein at least said microprocessor and said control unit are provided as mutually separate individual chip areas on a same semiconductor chip.
2 more elements
A processor system comprising:
- a memory having a mode register for identifying an operation mode wherein said memory operates in synchronism with a clock signal generated externally from said memory;
- a microprocessor providing operation mode information to be stored in said mode register of said memory;
- and
- a control unit coupled to said microprocessor and said memory, said control unit transferring said operation mode information to said mode register of said memory and operates in synchronism with said clock signal;
- wherein at least said microprocessor is provided as a first semiconductor chip area, and said control unit is provided as a second semiconductor chip area, on a single semiconductor chip.
2 more elements
Dependencies are inferred from the claim text.