Efficient data transfer mechanism for input/out devices having a device driver generating a descriptor queue and monitoring a status queue

A data transfer mechanism for use in a computer comprising:

• a memory;
• a descriptor queue position in said memory;
• a device driver that generates and loads entries in said descriptor queue, said entries at least indicating locations whereat data buffers are located in the memory;
• a single channel adapter;
• a bus operatively coupling the single channel adapter to the memory;
• a descriptor base address register positioned in the adapter;
• a descriptor count register positioned in the adapter;
• a descriptor current address register positioned in the adapter;
• a descriptor enqueue register positioned in the adapter wherein each of the registers is loaded with control information by said device driver at an initialization period;
• a memory, in said adapter, that temporarily stores descriptors;
• and
• a state machine that accesses selected ones of the registers and transfer multiple descriptors in a single burst mode from the descriptor queue to the memory based upon information contained in said selected ones of the registers.