Dynamic 3-level partial result merge adder

A system for performing an arithmetic operation on two N-nary operands including a 1-of-P first operand and a 1-of-Q second operand, comprising:

• a sum/bypass logic means for performing an arithmetic operation on one or more groupings of two or more bits of the 1-of-P first operand and one or more groupings of two or more bits of the 1-of-Q second operand to generate an intermediate sum and an HPG indicator;
• a control logic means, coupled to said sum/bypass logic means, for selecting said one or more groupings of two or more bits of the 1-of-P first operand and said one or more groupings of two or more bits of the 1-of-Q second operand for said arithmetic operation;
• an HPG logic means, coupled to said sum/bypass logic means, for generating a block HPG indicator;
• and
• a result logic means, coupled to said HPG logic means, for generating a 1-of-R final result, wherein said 1-of-R final result comprises said intermediate sum, and wherein said final result further comprises additional bits of said second operand when said intermediate sum comprises fewer bits than said second operand, such that said final result and said second operand comprise an equal number of bits, said additional bits of said second operand being selected according to said control logic.

A method to manufacture an apparatus that performs an arithmetic operation on two N-nary operands including a 1-of-P first operand and a 1-of-Q second operand, comprising:

• providing a sum/bypass logic that performs an arithmetic operation on one or more groupings of two or more bits of the 1-of-P first operand and one or more groupings of two or more bits of the 1-of-Q second operand to generate an intermediate sum and an HPG indicator;
• providing a control logic that selects said one or more groupings of two or more bits of the 1-of-P first operand and said one or more groupings of two or more bits of the 1-of-Q second operand for said arithmetic operation;
• coupling said sum/bypass logic to said control logic;
• providing an HPG logic that generates a block HPG indicator;
• coupling said HPG logic to said sum/bypass logic;
• providing a result logic that generates a 1-of-R final result, wherein said 1-of-R final result comprises said intermediate sum, and wherein said final result further comprises additional bits of said second operand when said intermediate sum comprises fewer bits than said second operand, such that said final result and said second operand comprise an equal number of bits, said additional bits of said second operand being selected according to said control logic;
• and
• coupling said result logic to said HPG logic.

A method to perform an arithmetic operation on two N-nary operands including a 1-of-P first operand and a 1-of-Q second operand, comprising:

• selecting one or more groupings of two or more bits of the 1-of-P first operand and one or more groupings of two or more bits of the 1-of-Q second operand;
• performing an arithmetic operation on said selected groupings to generate an intermediate sum and an HPG indicator;
• generating a block HPG indicator;
• and
• generating a 1-of-R final result, wherein said 1-of-R final result comprises said intermediate sum, and wherein said final result further comprises additional bits of said second operand when said intermediate sum comprises fewer bits than said second operand, such that said final result and said second operand comprise an equal number of bits, said additional bits of said second operand being selected according to said control logic.