Integrated digital loop carrier system with virtual tributary mapper circuit

A method of demapping signals from a synchronous transport signal format comprising virtual tributaries and overhead bytes for transmission over optical paths to a digital signal format for transmission over a wire path, comprising the steps of:

• receiving a synchronous transport signal and selecting at least one virtual tributary therefrom for processing;
• terminating said virtual tributary;
• processing said virtual tributary to obtain data, signaling and overhead bytes therefrom;
• generating at least a first control signal using said overhead bytes, and using said first control signal to control the storage of said data bytes in an elastic store having write and read sides, and to strobe the write side of an accumulator having write and read sides corresponding to the write and read sides of said elastic store, respectively, to increment its contents by the decimal value eight;
• generating a second control signal using at least said signaling bytes to strobe the write side of said accumulator and increment its contents by the decimal value one, and to store at least one bit in said elastic store indicating frame position of said digital signal within said virtual tributary;
• generating a third control signal representing a digital signal bit clock and selectively strobing said accumulator in accordance with said third control signal to decrement said accumulator contents by a decimal value one in accordance with the operation of the read side of said elastic store;
• and
• comparing the phase of the write side of said elastic store with the read side thereof using said accumulator contents and determining the phase difference between said virtual tributary and said digital signal being demapped therefrom at the elastic store.

A desynchronizing circuit for use when demapping a virtual tributary into a digital signal formatted in accordance with a frame, said desynchronizing circuit comprising a circuit for generating a synthesized clock for said demapped digital signal, said synthesized clock generating circuit comprising:

• a first divider and counter circuit for dividing a first clock signal using one of at least two values;
• and
• a second divider and counter circuit for determining which of said two values are used by said first divider and counter circuit to divide said first clock signal, said first divider and counter circuit operating in intervals distributed over the frame of said digital signal;
• wherein said first clock signal is substantially a 19.44 megahertz clock signal, said two values are 12 and 13, and said second divider and counter circuit comprises a divide-by-5 circuit and a divide-by-193 circuit;
• and
• wherein said divide-by-5 circuit and said divide-by-193 circuit are controlled so that three divide-by-13 operations and two divide-by-12 operations occur substantial every 5 count cycle throughout the frame when said divide-by-5 counter is clocked at said first clock signal speed.