US 6,333,935 B1Granted

State machine architecture with multiplexed random access memory

AssigneePMC-Sierra, Inc.

InventorsLarrie Simon Carr, Winston Ki-Cheong Mok

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Abstract

A plurality of time-division multiplexed data streams which are merged into a single data stream containing a plurality of data words and which are characterized by state vectors, are concurrently processed. The state vectors are stored in a read-write memory having a plurality of addressable memory locations. During an initial clock cycle, a pipeline receives an input data word from one of the data streams, an input state vector characterizing that data stream, and the memory location address of the input state vector. During one or more intermediate clock cycles, the pipeline processes the input data word and the input state vector to yield an output data word and an output state vector. During a final clock cycle, the pipeline transfers the output data word to an outgoing data stream, and transfers the output state vector into the aforementioned memory location address. A controller coupled to the memory and to the pipeline synchronizes operation thereof. A null cycle generator coupled to the pipeline and to the controller inserts null cycles into the concurrently processed data streams at regular time intervals and outputs a NULL signal to the controller during each null cycle. A multiplexer coupled between the controller and the memory multiplexes access to the memory between the controller/pipeline, and an alternate controller. Read access to the memory by the controller or pipeline is inhibited while the NULL signal is output, and write access to the memory by the pipeline is inhibited while an OUTGOING NULL replica of the NULL signal is being output by the pipeline during the final clock cycle. Accordingly, the alternate controller may gain read access to the memory while the NULL signal is output, and may gain write access to the memory while the OUTGOING NULL signal is output.

Apparatus for concurrently processing a plurality of time-division multiplexed data streams merged into a single data stream containing a plurality of data words and characterized by state vectors, said apparatus comprising:

(a) read-write memory means having a plurality of addressable memory locations for storing said state vectors;
(b) a pipeline for:
(i) during an initial clock cycle:
(1) receiving an input data word from one of said data streams;
(2) receiving, from a predefined memory location address in said memory means, an input state vector characterizing said one data stream;
(3) receiving said predefined memory location address of said input state vector;
(ii) during one or more intermediate clock cycles, processing said input data word and said input state vector to yield an output data word and an output state vector;
(iii) during a final clock cycle:
(1) transferring said output data word to an outgoing data stream;
(2) transferring said output state vector to said predefined memory location address in said memory means;
(c) control means coupled to said memory means and to said pipeline for synchronizing operation thereof;
(d) a null cycle generator coupled to said pipeline and to said control means, said null cycle generator for inserting null cycles into said concurrently processed data streams at regular time intervals and for outputting a NULL signal to said control means during each of said null cycles;
and,
(e) multiplexer means coupled between said control means and said read-write memory means for multiplexing access to said read-write memory means between:
(i) said control means and said pipeline;
and,
(ii) an alternate control means;
wherein said control means inhibits read access to said read-write memory means by said control means and by said pipeline during output of said NULL signal and inhibits write access to said read-write memory means by said pipeline during output of an OUTGOING NULL replica of said NULL signal by said pipeline during said final clock cycle, thereby enabling read access to said read-write memory means by said alternate control means during output of said NULL signal and enabling write access to said read-write memory means by said alternate control means during output of said OUTGOING NULL signal.

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Abstract

Claims11