Semiconductor storage device
AssigneeOki Electric Industry Co., Ltd.
InventorsAkira Nakayama, Yuichi Matsushita
Life of this patent
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Abstract
The present invention implements a decrease in chip size. The device is comprised of memory cell arrays 34a and 34b, a bank selector 36, a cell select circuit 38a, a data multiplexer 40, and an input/output buffer 42. The bank selector generates a bank select signal and selects the memory cell arrays alternately. The cell select circuit selects a predetermined memory cell of the memory cell array selected by the bank select signal and performs a read operation from and a write operation to this memory cell. The data multiplexer transfers the read data from the memory cell array selected by the bank select signal to the input/output buffer.
Claims12
A semiconductor storage device which performs read and write operations of data synchronizing with the cycle unit of a clock signal, comprising two memory cell arrays, wherein at one cycle after a read operation from a memory cell at a predetermined address of one of said memory cell arrays, a write operation is performed to the memory cell at the same address of said memory cell array, and a read operation is also performed to a memory cell at a predetermined address of said other memory cell array, and
- wherein the memory cell to be read out in said one of the memory cell arrays is selected by address information generated relating to a bank select signal, and the memory cell to be written to in said other memory cell array is selected by said address information.
A semiconductor storage device which performs read and write operations of data synchronizing with the cycle unit of a clock signal, comprising two memory cell arrays, wherein at one cycle after a read operation from a memory cell at a predetermined address of one of said memory cell arrays, a write operation is performed to the memory cell at the same address of said memory cell array, and a read operation is also performed to a memory cell at a predetermined address of said other memory cell array, and
- an array select circuit, a cell select circuit, a data transfer circuit and an input/output buffer, wherein said array select circuit generates an array select signal for selecting said memory cell arrays alternately, said cell select circuit selects a predetermined memory cell of said memory cell array selected by said array select signal and performs a read operation from and a write operation to this memory cell, and said data transfer circuit transfers the read data from said memory cell array selected by said array select signal to said input/output buffer.
A semiconductor storage device which performs read and write operations of data synchronizing with the cycle unit of a clock signal, comprising two memory cell arrays, wherein at one cycle after a read operation from a memory cell at a predetermined address of one of said memory cell arrays, a write operation is performed to the memory cell at the same address of said memory cell array, and a read operation is also performed to a memory cell at a predetermined address of said other memory cell array, and
- an array select circuit, a cell select circuit, a data transfer circuit, an input/output buffer and an input/output data amplifier, wherein
- said array select circuit generates an array select signal for alternately selecting said memory cell arrays,
- said cell select circuit selects a predetermined memory cell of said memory cell array selected by said array select signal, and performs a read operation from and a write operation to this memory cell,
- said data transfer circuit performs processing for transferring the read data from said memory cell array selected by said array select signal to said input/output data amplifier, and processing for transferring the write data sent from said input/output data amplifier to said predetermined memory cell array, and
- said input/output data amplifier amplifies the write data which is sent from said input/output buffer to said data transfer circuit, and the read data which is sent from said data transfer circuit to said input/output buffer.
Dependencies are inferred from the claim text.