Method and apparatus for crossing clock domain boundaries
AssigneeMicron Technology, Inc.
InventorsBrent Keeth, Brian Johnson
Life of this patent
Estimating the term…
Abstract
A method and apparatus that expands the data envelope of captured data to a predetermined number of clocks cycles. The predetermined number of clock cycles is large enough to ensure that an internally generated master clock edge remains within the data envelope over the entire operating range. This way, captured data remains valid and can be properly transferred to the master clock domain from a capture clock domain despite temperature and voltage variations that may effect the timing of the memory device.
Claims33
A memory device comprising:
- a plurality of first circuits, each first circuit having a first input for receiving a first clock signal and a second input for receiving a respective first input signal, each first circuit being controllable to latch its respective first input signal such that the first input signal has a data envelope corresponding to N number of cycles of the first clock signal, where N>1, each first circuit having at least one first output signal corresponding to the latched first input signal;
- and
- a re-timing circuit coupled to said plurality of first circuits, said re-timing circuit having a third input for receiving a second clock signal, said re-timing circuit receiving said at least one first output signal from said first circuits and outputting re-timed first output signals in accordance with transitions of the second clock signal.
A processor system comprising:
- a processor;
- and
- memory device coupled to said processor, said memory device comprising:
- a plurality of first circuits, each first circuit having a first input for receiving a first clock signal and a second input for receiving a respective first input signal, each first circuit being controllable to latch its respective first input signal such that the first input signal has a data envelope corresponding to N number of cycles of the first clock signal, where N>1, each first circuit having at least one first output signal corresponding to the latched first input signal;
- and
- a re-timing circuit coupled to said plurality of first circuits, said re-timing circuit having a third input for receiving a second clock signal, said re-timing circuit receiving said at least one first output signal from said first circuits and outputting re-timed first output signals in accordance with transitions of the second clock signal.
A method of operating a memory device, said method comprising the steps of:
- receiving a plurality of first input signals responsive to a first clock signal;
- latching the received first input signals such that each latched input signal has a data envelope corresponding to N number of cycles of the first clock signal, where N>1;
- and
- outputting re-timed first input signals in accordance with transitions of a second clock signal, wherein the data envelope of each latched first input signal ensures that the latched first input signals are valid when re-timed.
Dependencies are inferred from the claim text.