Synchronous semiconductor memory device capable of selecting column at high speed

A synchronous semiconductor memory device comprising:

• command decode circuitry for receiving and decoding an externally supplied command asynchronously with a clock signal, to activate a column access mode instruction signal when the received command is an access command designating a column access;
• first circuitry for taking and latching said column access mode instruction signal from said command decode circuitry in synchronization with said clock signal to generate a column address activation signal;
• first address generating circuitry for generating an internal column address signal from an externally supplied address signal according to the column address activation signal from said first circuitry;
• column control circuitry for generating a column selection activation signal activated over a period of a prescribed number of cycles of said clock signal in response to said column access mode instruction signal;
• second circuitry for generating a counter address activation signal in synchronization with said clock signal in response to activation of said column selection activation signal and inactivation of said column access mode instruction signal;
• a counter for performing a counting operation in a prescribed sequence in synchronization with said clock signal with said externally supplied address signal being a starting count value;
• and
• second address generating circuitry for taking an output count value from said counter in response to said counter address activation signal to generate the internal column address signal, the first and second address generating circuitry sharing an output stage.