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US 6,333,889 B1Granted
Logic-merged semiconductor memory having high internal data transfer rate
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorKazutami Arimoto
Life of this patent
Estimating the term…
Abstract
Two memory sub arrays are provided adjacent to a read/write circuit. An internal data line pair corresponding to the memory sub array located farther away is connected to the read/write circuit via a feed-through line pair (FLP) located at an upper layer above the memory sub array located closer. The internal data line pair for the memory sub array located closer is coupled to the read/write circuit. The number of bits of the internal data transfer can be increased by carrying out column selection simultaneously under the state where the word lines are selected simultaneously in the two memory sub arrays. The internal data transfer rate in a semiconductor memory device is increased.
Claims21
A semiconductor memory device comprising:
- a plurality of memory blocks divided into first and second sub arrays along a column direction, each memory block including a plurality of memory cells arranged in rows and columns;
- a plurality of sense amplifier circuits provided corresponding to columns in said plurality of memory blocks for sensing and amplifying memory cell data of corresponding columns when activated;
- a plurality of internal data lines arranged extending along the column direction, each internal data line being provided corresponding to a predetermined number of sense amplifier circuits per one memory block, said plurality of internal data lines including a first group of the internal data lines provided for said first sub array and a second group of the internal data lines provided for said second sub array, the first group including a feed-through line arranged extending in the column direction over said second sub array and formed at an interconnection layer differing from an interconnection layer of the second group;
- and
- a plurality of column select circuits provided corresponding to the respective sense amplifier circuits and the respective internal data lines for coupling corresponding sense amplifier circuits to corresponding internal data lines according to a column select signal.
2 more elements
A semiconductor memory device comprising:
- a plurality of memory blocks each including a plurality of memory cells arranged in rows and columns;
- a plurality of word lines provided corresponding to respective rows of memory cells, each word line being connected to memory cells of a corresponding row connected;
- a plurality of sense amplifier circuits provided corresponding to the columns in said plurality of memory blocks, for sensing and amplifying memory cell data of corresponding columns when activated;
- a plurality of internal data lines each provided corresponding to a predetermined number of the sense amplifier circuits per one memory block and extending in a column direction over said plurality of memory blocks;
- row select circuitry, for driving word lines arranged corresponding to addressed rows to a selected state simultaneously in a prescribed number of memory blocks in said plurality of memory blocks according to a row address signal;
- column specify signal generation circuits provided corresponding to said plurality of memory blocks, each for generating a column specify signal specifying a column in a specified memory block according to a column address signal and a memory block specify address signal applied simultaneously;
- and
- a plurality of column select circuits provided corresponding to the respective sense amplifier circuits, for coupling the respective sense amplifier circuits of corresponding columns to corresponding internal data lines in response to said column specify signal.
5 more elements
A semiconductor memory device comprising:
- a plurality of memory blocks each including a plurality of memory cells arranged in rows and columns;
- a plurality of sense amplifier circuits provided corresponding to the columns in said plurality of memory blocks, for sensing and amplifying data of memory cells of corresponding columns when activated;
- a plurality of internal data lines arranged extending along a column extending direction, each internal data line provided corresponding to a predetermined number of sense amplifier circuits per one memory block, and constituting a single end signal line;
- and
- a plurality of column select circuits provided corresponding to said plurality of sense amplifier circuits respectively and said plurality of internal data lines, for coupling corresponding sense amplifier circuits to corresponding internal data lines according to a column select signal.
2 more elements
A semiconductor memory device comprising:
- a plurality of memory blocks each including a plurality of memory cells arranged in rows and columns, the memory blocks being divided into a plurality of banks that can drive a row to a selected state independent of each other;
- a plurality of row select circuits provided corresponding to said plurality of banks respectively, each for driving, when a corresponding bank is addressed according to a bank address signal specifying a bank and a row address signal specifying a row applied simultaneously, a plurality of addressed rows simultaneously to a selected state in said corresponding bank;
- a plurality of column select circuits provided corresponding to said plurality of banks, each column select circuit for selecting a plurality of columns simultaneously in a corresponding bank according to a bank address signal and a column address signal applied simultaneously;
- and
- a plurality of internal data lines provided extending in a column direction common to said plurality of banks, and coupled to the plurality of columns selected by said plurality of column select circuits.
2 more elements
A semiconductor memory device comprising:
- a plurality of first memory blocks each including a plurality of memory cells arranged in rows and columns, the first memory blocks being divided into first and second sub arrays along a column direction;
- a plurality of second memory blocks each including a plurality of memory cells arranged in rows and columns, the second memory blocks being divided into third and fourth sub arrays along the column direction;
- a plurality of sense amplifier circuits provided corresponding to the columns in the first and second memory blocks, for sensing and amplifying data on corresponding columns when activated;
- a plurality of first internal data lines extending along the column direction, each first internal data line being provided corresponding to a predetermined number of sense amplifier circuits per one first memory block, said plurality of first internal data lines including a first group of internal data lines provided for said first sub array and a second group of internal data lines provided for said second sub array, the first group including a first feed-through line arranged extending along the column direction over said second sub array and formed at an interconnection layer differing from an interconnection layer of the second group;
- a plurality of second internal data lines extending along the column direction, each second internal data line being provided corresponding to a predetermined number of sense amplifier circuits per one second memory block, said plurality of second internal data lines including a third group of internal data lines provided for said third sub array and a fourth group of internal data lines provided for said fourth sub array, the fourth group including a second feed-through line arranged extending along the column direction over said third sub array and formed at an interconnection layer differing from an interconnection layer of the third group;
- a plurality of first column select circuits provided corresponding to the columns of said first memory blocks and to said plurality of first internal data lines, for coupling corresponding columns to corresponding first internal data lines according to a first column specify signal;
- a plurality of second column select circuits provided corresponding to the columns of said second memory blocks and to said plurality of second internal data lines, for coupling corresponding columns to corresponding second internal data lines according to a second column specify signal;
- and
- a read/write circuit arranged between said plurality of first memory blocks and said plurality of second memory blocks and coupled to the first and second internal data lines for data transfer.
6 more elements
A semiconductor memory device comprising:
- a plurality of memory block each including a plurality of memory cells arranged in rows and columns;
- a plurality of sense amplifier circuits provided corresponding to the columns in said plurality of memory blocks, for sensing and amplifying memory cell data of corresponding columns when activated;
- a plurality of internal data lines extending along a column extending direction, each internal data line being provided corresponding to a predetermined number of sense amplifier circuits per one memory block;
- a plurality of column select circuits provided corresponding to said plurality of sense amplifier circuits and to said plurality of internal data lines, for coupling corresponding sense amplifier circuits to corresponding internal data lines according to a column specify signal;
- an internal clock generation circuit for receiving an externally applied clock signal to generate an internal clock signal of multiple phases;
- and
- a column select signal generation circuit operating in synchronization with each phase of the multiple phases of said internal clock signal for generating and providing to said plurality of column select circuits the column specify signal according to an applied signal in synchronization with said external clock signal.
4 more elements
Dependencies are inferred from the claim text.