Semiconductor memory device

A semiconductor memory device comprising:

• a plurality of word lines,
• a plurality of bit lines,
• a plurality of memory cells each being mounted in a matrix form at a point of intersection between each of said word lines and bit lines;
• a plurality of input/output lines each being mounted corresponding to each of said bit lines used to input and output data fed from outside to said corresponding memory cell,
• memory cell arrays each having a plurality of column switches to connect said corresponding bit lines to said corresponding input/output lines;
• row decoders to activate any one of said plurality of word lines;
• a plurality of banks each having a column decoder to activate any one of said plurality of column switches;
• a refresh counter to renew its counter value in accordance with a refresh command;
• first controlling means for outputting a first controlling signal to activate any one of said row decoders of said plurality of banks based on renewed counter values every time said refresh command is supplied;
• and
• second controlling means for outputting a second controlling signal to activate column decoders of all banks based on a write command or read command supplied after said refresh command has been supplied.