Self-refresh controlling apparatus
AssigneeHyundai Electronics Industries Co., Ltd.
InventorsKwang-Rae Cho, Joon-Ho Kim
Life of this patent
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Abstract
A self refresh controlling apparatus for use in a semiconductor memory device includes a delay unit for delaying the clock buffer enable control signal by a predetermined time and an internal clock signal activation controller for controlling activation of the internal clock signal by logically combining the internal clock signal with a control signal generated under control of the delayed clock buffer enable control signal from the delaying unit and the internal clock signal in order to prevent mis-operation due to the internal clock signal generated late in completion of self refresh operation.
Claims6
A self refresh controlling apparatus comprising;
- a first buffering means for buffering a clock enable signal received from an external source to generate a self refresh completion control signal;
- a self refresh logic means for controlling activation of a clock buffer enable control signal by performing a self refresh operation depending on the state of the self refresh completion control signal from the first buffering means;
- a second buffering means receiving the clock buffer enable control signal for comparing a potential of an external clock signal with a reference potential to generate an internal clock signal;
- a delaying means for delaying the clock buffer enable control signal by a predetermined time;
- an internal clock signal activation controlling means for controlling activation of the internal clock signal by logically combining the internal clock signal with a control signal generated under control of the delayed clock buffer enable control signal from the delaying means and the internal clock signal;
- and
- a latching means for latching, in synchronization with the external clock signal, a command and an address buffered by the internal clock signal of which timing is adjusted at the internal clock signal activation controlling means.
A self refresh controlling apparatus comprising;
- a first buffer constructed and arranged to buffer a clock enable signal received from an external source to generate a self refresh completion control signal;
- self refresh logic constructed and arranged to control activation of a clock buffer enable control signal by performing a self refresh operation depending on the state of the self refresh completion control signal from the first buffer;
- a second buffer constructed and arranged to receive the clock buffer enable control signal for comparing a potential of an external clock signal with a reference potential to generate an internal clock signal;
- a delay circuit constructed and arranged to delay the clock buffer enable control signal by a predetermined time;
- an internal clock signal activation controller constructed and arranged to controlling activation of the internal clock signal by logically combining the internal clock signal with a control signal generated under control of the delayed clock buffer enable control signal from the delay circuit and the internal clock signal;
- and
- a latch constructed and arranged to latch, in synchronization with the external clock signal, a command and an address buffered by the internal clock signal of which timing is adjusted at the internal clock signal activation controller.
Dependencies are inferred from the claim text.