Semiconductor memory device permitting improved integration density and reduced accessing time
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsHiroshi Kato, Tsukasa Ooishi, Hideto Hidaka
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Abstract
A sub-amplifier includes first and second transistors which each receive the potential of a sub-I/O line pair at each gate, a third transistor controlled by a signal transmitted in the memory cell column-direction and coupling the sources of the first and second transistors and a ground potential, and fourth and fifth transistors controlled by a signal transmitted in the memory cell row-direction and coupling the drains of the first and second transistors and a main I/O line pair. Since the sub-amplifier is controlled by a signal transmitted in the column-direction, the influence of skew with a column selecting signal can be reduced.
Claims12
A semiconductor memory device, comprising:
- a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns, said memory cell array including a plurality of memory cell blocks;
- a row selecting circuit responsive to an address signal for selecting a memory cell row;
- a column selecting circuit responsive to said address signal for outputting a column selecting signal to select a memory cell column and a column-related control signal;
- a plurality of first signal lines for transmitting said column selecting signal in a direction of said memory cell columns;
- a plurality of second signal lines, provided in parallel with said first signal lines, for transmitting said column-related control signal;
- a plurality of sense amplifiers provided corresponding to memory cell columns in each said memory cell block;
- a plurality of sub-data line pairs provided corresponding to said plurality of memory cell blocks;
- a selecting gate circuit responsive to said column selecting signal for selectively transmitting data read out from a sense amplifier corresponding to the selected memory cell column to said sub-data line pair;
- a main data line pair provided in common to said plurality of memory cell blocks;
- and
- a plurality of sub-amplifier circuits for transmitting read data received from said sub-data line pairs to said main data line pair,
- each said sub-amplifier circuit including,
- first and second MOS transistors, provided for lines of said main data line pair respectively, for selectively discharging one line out of said main data line pair from a second potential to a first potential in response to a potential level of the corresponding sub data line pair, and
- an activating circuit responsive to said column-related control signal for activating the discharging operation of said first and second MOS transistors.
Dependencies are inferred from the claim text.