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US 6,333,882 B1Granted
Equilibration/pre-charge circuit for a memory device
AssigneeMicron Technology, Inc.
InventorsTodd A. Merritt, George B. Raad, Charles L. Ingalls
Life of this patent
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Abstract
An equilibration circuit for a memory device that prevents excessive current from being drawn by the memory device when a row to column short exists while still allowing the use of segmented column repair is disclosed. Each equilibration circuit of a memory device is connected to the equilibration voltage through a transistor that is controlled by a pulsed signal. When the pulsed signal is high, the transistor will turn on, connecting the digital lines to the equilibration voltage to pre-charge the digit lines to the equilibration voltage. The pulse duration is short enough, however, to turn the transistor off before the equilibration voltage can be pulled down if a column to row short exists.
Claims55
An equilibration circuit for a memory device comprising:
- a first transistor having a first terminal adapted to be connected to a first digit line of said memory device, a gate terminal adapted to receive a first control signal, and a second terminal;
- a second transistor having a first terminal connected to said second terminal of said first transistor, a gate terminal adapted to receive said first control signal, and a second terminal adapted to be connected to a second digit line of said memory device;
- a third transistor having a first terminal connected to said first terminal of said second transistor, a second terminal adapted to be connected to a voltage potential, and a gate terminal adapted to receive a second control signal;
- and
- a pulse generator to generate said second control signal,
- wherein said second control signal is a pulsed signal having a predetermined duration, and said third transistor in response to said pulsed signal turns on for said predetermined duration and then turns off, to connect said first terminal of said second transistor and said second terminal of said first transistor to said voltage potential.
3 more elements
A circuit for pre-charging a first and second digit line of a memory device to a voltage potential comprising:
- a switch having a first terminal connect able to said first and second digit lines and a second terminal connected to said voltage potential,
- wherein said switch is turned on for a predetermined duration and then turned off, said switch when turned on connecting said voltage potential to said first and second digit lines and pre-charging said first and second digit lines to said voltage potential.
A memory device comprising:
- a plurality of memory arrays, each of said plurality of memory arrays having a plurality of memory cells arranged in rows and columns;
- a plurality of pairs of digit lines, each of said plurality of pairs of digit lines associated with a column of said plurality of memory cells;
- and
- a plurality of equilibration circuits, each of said plurality of equilibration circuits being associated with at least one pair of said plurality of pairs of digit lines, each of said plurality of equilibration circuits comprising:
- a first transistor having a first terminal connectable to a first digit line of one of said pairs of digit lines and a second digit line of said one of said pairs of said digit lines, a second terminal connected to a voltage potential, and a gate terminal connected to a control signal line to receive a first control signal;
- and
- a pulse generator connected to said control signal line, said pulse generator generating said first control signal,
- wherein said first control signal is a pulsed signal having a predetermined duration, and said first transistor in response to said pulsed signal turns on for a predetermined duration and then turns off again, said first transistor when turned on connecting said first and second digit lines of said one of said pairs of digit lines to said voltage potential to pre-charge said first and second digit lines to said voltage potential.
5 more elements
A processing system comprising:
- a processing unit;
- and
- a memory device connected to said processing unit, said memory device comprising:
- a plurality of memory arrays, each of said plurality of memory arrays having a plurality of memory cells arranged in rows and columns;
- a plurality of pairs of digit lines, each of said plurality of pairs of digit lines associated with a column of said plurality of memory cells;
- and
- a plurality of equilibration circuits, each of said plurality of equilibration circuits being associated with at least one pair of said plurality of digit lines, each of said plurality of equilibration circuits comprising:
- a first transistor having a first terminal connectable to a first digit line of one of said pairs of digit lines and a second digit line of said one of said pairs of said digit lines, a second terminal connected to a voltage potential, and a gate terminal connected to a control signal line to receive a first control signal;
- and
- a pulse generator connected to said control signal line, said pulse generator generating said first control signal,
- wherein said first control signal is a pulsed signal having a predetermined duration, and said first transistor in response to said pulsed signal turns on for a predetermined duration and then turns off again, said first transistor when turned on connecting said first and second digit lines of said one of said pairs of digit lines to said voltage potential to pre-charge said first and second digit lines to said voltage potential.
8 more elements
A method for charging a plurality of digit lines of a memory device to a voltage potential comprising:
- supplying a pulsed control signal to turn on a switch having a first terminal connectable to said plurality of digit lines and a second terminal connected to said voltage potential to connect said plurality of digit lines to said voltage potential for a predetermined period of time;
- charging said plurality of digit lines to said voltage potential;
- and
- turning off said switch to disconnect said digit lines from said voltage potential after said predetermined period of time.
1 more element
Dependencies are inferred from the claim text.