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US 6,333,877 B1Granted
Static type semiconductor memory device that can suppress standby current
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsHideaki Nagaoka, Kiyoyasu Akai
Life of this patent
Estimating the term…
Abstract
A memory cell power supply line is provided to supply a ground potential corresponding to each column in a regular memory cell array. Among fuse elements, the fuse element corresponding to the memory cell column that is to be subjected to redundancy replacement is decoupled, whereby supply of the ground potential to the regular memory cell column to be replaced is suppressed.
Claims14
A static type semiconductor memory device comprising:
- a regular memory cell array in which a plurality of memory cells are arranged in a matrix, each memory cell capable of retaining a first level and a second level,
- said regular memory cell array being divided in a plurality of memory cell replacement units;
- a redundant memory cell array for redundancy repair for one of said memory cell replacement units in said regular memory cell array;
- a power supply node to which a first potential corresponding to said first level is supplied;
- a plurality of first lines, provided corresponding to said memory cell replacement units respectively, each for supplying said first potential from said power supply node to said memory cells in a corresponding said memory cell replacement unit;
- and
- a potential supply control circuit that can selectively cease supply of said first potential from said power supply node to one of said plurality of first lines;
- wherein said power supply control circuit comprises a potential modify circuit that can modify the potential supplied to said plurality of first lines to a second potential corresponding to said second level from said first potential independently and in a nonvolatile manner.
5 more elements
A static type semiconductor memory device comprising:
- a regular memory cell array in which a plurality of memory cells are arranged in a matrix, each memory cell capable of retaining a first level and a second level,
- said regular memory cell array being divided into a plurality of memory cell replacement units;
- a redundant memory cell array to perform redundancy repair for one of said memory cell replacement units in said regular memory cell array;
- a power supply node to which a first potential corresponding to said first level is supplied;
- a plurality of first lines provided corresponding to said memory cell replacement units respectively, each for supplying said first potential from said power supply node to said memory cells in a corresponding one of said memory cell replacement units in a normal operation;
- and a plurality of potential retain circuits provided corresponding to said plurality of first lines, respectively, each for precharging a corresponding one of said first lines to a second potential corresponding to said second level after initiation of power supply to said static type semiconductor memory device, and supplying said first potential to said corresponding one of first lines in response to said corresponding memory cell replacement unit being accessed.
3 more elements
Dependencies are inferred from the claim text.