Semiconductor memory device

A semiconductor memory device formed on a semiconductor substrate, comprising:

• a memory cell array including a plurality of memory cell groups arranged in a plurality of rows or columns, each of the memory cell groups having a plurality of memory cells lined in a row or column, and a redundant cell group having a plurality of redundant cells arranged in parallel with the memory cell groups;
• a plurality of cell selection lines for selecting a specific memory cell group out of the plurality of memory cell groups;
• a redundant cell selection line for selecting the redundant cell group;
• a cell selection circuit for outputting decode signals and allowing one cell selection line out of the plurality of cell selection lines to select the specific memory cell group based on an external signal;
• defective cell designation means for outputting defective cell designation signals designating a pre-detected defective cell out of the plurality of memory cells;
• and
• connection change means for electrically disconnecting the cell selection line selecting the memory cell group including the defective cell from the cell selection circuit and outputting an output signal from the cell selection circuit to the redundant cell group, the connection change means shifting connection between each of the decode signals and associated one of either the plurality of cell selection lines or the redundant cell selection line in response to an associated one of the defective cell designation signals;
• wherein the defective cell designation means comprises:
• a plurality of defective cell designation circuits for outputting encoded designation signals capable of designating the plurality of cell selection lines;
• and
• a defective cell designation signal generation circuit for decoding the encoded designation signals and generating the defective cell designation signals.