Semiconductor circuit with adjustment of double data rate data latch timings
AssigneeFujitsu Limited
InventorNaoharu Shinozaki
Life of this patent
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Abstract
A semiconductor circuit which receives a strobe signal and a data signal includes a latch-signal-generation circuit which generates a first latch signal delayed by a first delay time relative to the strobe signal and a second latch signal inverted and delayed by a second delay time relative to the strobe signal, a control circuit which adaptively controls the latch-signal-generation circuit to adjust timings of the first and second latch signals such that the first delay time and the second delay time become substantially equal, and a latch circuit which latches the data signal at edge timings of the first and second latch signals.
Claims11
A semiconductor circuit which receives a strobe signal and a data signal, comprising:
- a latch-signal-generation circuit which generates a first latch signal delayed by a first delay time relative to the strobe signal and a second latch signal inverted and delayed by a second delay time relative to the strobe signal;
- a control circuit which adaptively controls said latch-signal-generation circuit to adjust timings of the first and second latch signals such that the first delay time and the second delay time become substantially equal;
- and
- a latch circuit which latches the data signal at edge timings of the first and second latch signals.
A semiconductor circuit, which receives a strobe signal and a data signal, comprising:
- a latch-signal-generation circuit which generates a first latch signal delayed relative to the strobe signal by a first delay time measured from a first-type edge of the strobe signal to a corresponding edge of the first latch signal, and generates a second latch signal inverted and delayed relative to the strobe signal by a second delay time measured from a second-type edge of the strobe signal to a corresponding edge of the second latch signal, the first-type edge being one of a rising edge and a falling edge and the second-type edge being another one of the rising edge and the falling edge;
- a latch circuit which latches the data signal at edge timings of the first and second latch signals;
- and
- a control circuit which adaptively controls said latch-signal-generation circuit to adjust timings of the first and second latch signals such that the first delay time and the second delay time become substantially equal.
Dependencies are inferred from the claim text.