Semiconductor memory device having normal and standby modes, semiconductor integrated circuit and mobile electronic unit
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorHiroyuki Yamauchi
Life of this patent
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Abstract
In a standby mode, a word driver supplies a negative voltage onto its associated word line, and a precharge circuit electrically disconnects its associated pair of bit lines from power supply nodes receiving a supply voltage. In this manner, access transistors, connected to L- or H-level data retention nodes, can have their source-drain voltage lowered to such a level as eliminating a GIDL current. As a result, the amount of current dissipated in the standby mode can be reduced without causing the GIDL current problem.
Claims13
A semiconductor memory device having a normal mode and a standby mode, the device comprising:
- an array of memory cells arranged in columns and rows;
- a plurality of word lines, each being associated with one of the rows;
- a plurality of bit lines, each being associated with one of the columns;
- a plurality of access transistors, each being provided for an associated one of the memory cells, connected between a data retention node of the associated memory cell and one of the bit lines that is associated with the memory cell, and receives, at its gate, a voltage on one of the word lines that is associated with the memory cell;
- and
- potential difference generating means for generating a negative potential difference between the gate and source of one of the access transistors while the device is in the standby mode, the access transistor being connected to a data retention node storing logical-one-level or logical-zero-level data thereon.
A semiconductor memory device having a normal mode and a standby mode, the device comprising:
- an array of memory cells arranged in columns and rows;
- a plurality of word lines, each being associated with one of the rows;
- a plurality of bit lines, each being associated with one of the columns;
- a plurality of access transistors, each being provided for an associated one of the memory cells, connected between a data retention node of the associated memory cell and one of the bit lines that is associated with the memory cell, and receives, at its gate, a voltage on one of the word lines that is associated with the memory cell;
- word line driving means for activating one of the word lines, the word line being associated with one of the memory cells that is to be accessed;
- and
- precharge means for precharging the bit lines to a supply voltage level during a predetermined period before the memory cell is accessed,
- wherein while the device is in the standby mode,
- the word line driving means supplies a negative voltage onto the word lines, and
- the precharge means electrically disconnects the bit lines from a power supply node receiving a supply voltage.
Dependencies are inferred from the claim text.