Semiconductor memory device having selectively shielded data lines
AssigneeOki Electric Industry Co., Ltd.
InventorHitoshi Doi
Life of this patent
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Abstract
A semiconductor memory device having a data bus connecting a differential amplifier circuit of a memory cell array, which uses the differential amplifier circuit as input/output terminals of data to the selected memory cells out of a plurality of memory cells, with a plurality of input/output pads for writing and reading data to and from the memory cells. The data bus has a plurality of write data lines and a plurality of read data lines. The write and read data lines of the data bus are arranged in parallel with one another. The two kinds of data lines are arranged alternately in the direction in which they are arranged, and one kind of the data lines serves as the shielding lines for the other other kind of data lines.
Claims14
A semiconductor memory device comprising:
- a memory cell array having a plurality of memory cells on a semiconductor substrate, wherein said memory cell array includes a differential amplifier circuit serving as data input/output terminals of said memory cell array when data is written in or read from a selected memory cell;
- a plurality of input/output pads, provided on said semiconductor substrate, for writing data to said memory cells and reading data from said memory cells;
- and
- a data bus that connects said differential amplifier and said input/output pads, wherein said data bus includes a plurality of write data lines dedicated for writing data to said memory cells and a plurality of read data lines dedicated for reading data from said memory cells, wherein said plurality of write data lines have mutually parallel portions and said plurality of read data lines have mutually parallel portions, wherein at least said parallel portions of said write data lines are arranged alternately with said read data lines in an arrangement direction of said parallel portions on said semiconductor substrate, and wherein said write data lines are held at a predetermined potential level when data is read and said read data lines are held at the predetermined potential level when writing data, to respectively function as shielded lines.
A semiconductor memory device comprising:
- a memory cell array which has a plurality of memory cells and a differential amplifier circuit, the differential amplifier circuit amplifying read data from a memory cell and write data to be written into the memory cell;
- a plurality of input/output pads which receive the write data and the read data;
- and
- a data bus, coupled between the differential amplifier circuit and said input/output pads, which includes a plurality of write data lines transferring the write data and a plurality of read data lines transferring the read data,
- wherein said write data lines and said read data lines have mutually parallel portions, wherein at least the parallel portions of said write data lines are arranged alternately with said read data lines in an arrangement direction of said parallel portions, wherein said write data lines are held at a predetermined potential level when said read data lines transfer the read data, and wherein said read data lines are held at the predetermined potential level when said write data lines transfer the write data.
A method of shielding a data bus of a semiconductor memory device, the semiconductor memory device including a memory cell array having a plurality of memory cells and differential amplifiers coupled to the memory cells,
- the data bus including pairs of read data lines and pairs of write data lines having portions thereof mutually parallel with respect to each other and being coupled between the differential amplifiers and input/output terminals of the semiconductor memory device, the method comprising:
- holding the pairs of read data lines to a predetermined potential level during writing of data into the memory cell array;
- and
- holding the pairs of write data lines to the predetermined potential level during reading of data from the memory cell array.
Dependencies are inferred from the claim text.