Built-in self-test for analog to digital converter
AssigneeInternational Business Machines Corporation
InventorsBrooks A. Cummings, Douglas R. Firth, Donald L. Wheater
Life of this patent
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Abstract
An on-chip analog to digital converter (ADC) test circuit comprises a waveform generator for developing a known arbitrary waveform. A switch selectively connects the waveform generator to the ADC in a test mode or an internal analog input to the ADC in an operate mode. In the test mode the ADC develops a known sequence of digital codes. A signature register is connected to an output of the ADC for receiving and compressing the sequence of digital codes during the test mode. The register develops a single compressed signature representative of the entire ADC digital output sequence. The compression method may be used to test ADC monotonicity, linearity, and that there are no missing codes.
Claims22
An on-chip analog to digital converter (ADC) test circuit comprising:
- a waveform generator for developing a known arbitrary waveform;
- switch means for selectively connecting the waveform generator to the ADC in a test mode or an internal analog input to the ADC in an operate mode, whereby in the test mode the ADC develops a known sequence of digital codes;
- a signature register connected to an output of the ADC for receiving and compressing the sequence of digital codes output from the ADC during the test mode and developing an output representative of the compressed sequence.
A built in self test circuit on an electronic circuit chip including an analog to digital converter (ADC) that converts an analog signal to a corresponding digital code, comprising:
- a waveform generator for developing a known arbitrary analog signal;
- a switch selectively connecting either the waveform generator to an input of the ADC in a test mode or an internal analog input to the ADC input in an operate mode, whereby in the test mode the ADC develops a known sequence of digital codes;
- a signature register connected to an output of the ADC for receiving and compressing the sequence of digital codes output from the ADC during the test mode and developing an output representative of the compressed sequence.
Dependencies are inferred from the claim text.