Coding/decoding system of bit insertion/manipulation line code for high-speed optical transmission system

A decoding apparatus of bit insertion/manipulation line code comprising:

• disparity calculating means for calculating a disparity with respect to received codeword RD[m+1:1];
• m+1 bit register means for separating upper m-bits of the received codeword from an insertion bit that was inserted during coding;
• block inversion check means for checking for a bit inversion with respect to the upper m-bits of the received codeword, and producing a block control signal;
• block inversion means for performing a selective block inversion with respect to the upper m-bits of the received codeword according to the block control signal;
• bit manipulation check means for checking for a bit manipulation with respect to a block output from said block inversion means, and producing a bit control signal for recovering to information data prior to coding;
• and
• bit manipulation means for performing an inverse manipulation of coding with respect to the block output from the block inverting means in response to the bit control signal to thereby recover the information data.

A coding/decoding system, comprising:

• an encoder provided at one end of a transmission system for bit insertion/manipulation line code, said encoder comprising:
• a disparity calculator arranged to calculate a disparity with respect to m-bit information data;
• an insertion bit generator arranged to generate an insertion bit for minimizing a disparity of the m+1 bit information data in response to the disparity from said disparity calculator;
• an m+1 bit register arranged to provide m+1 bit blocks PCD[m+1:1] pre-coded by using the applied m-bit information data and the insertion bit;
• a bit manipulation controller arranged to produce a bit control signal for bit manipulation in order to minimize a digital sum variation (DSV) according to the applied m-bit information data and the disparity from said disparity calculator;
• a bit manipulator arranged to manipulate a part of bits of the m+1 bit blocks pre-coded according to the bit control signal, and produce a codeword CD[m+1:1];
• a block inversion controller arranged to produce a block control signal for block inversion in order to maintain a running digital sum (RDS) according to the disparity from said disparity calculator;
• and
• a block inverter arranged to perform a selective block inversion with respect to the codeword CD[m+1:1] according to the block control signal, and produce inverted data ID[m+1] as a codeword for transmission;
• and
• a decoder provided at the other end of said transmission system for bit insertion/manipulation line code, said decoder comprising:
• a disparity calculator arranged to calculate a disparity with respect to a received codeword RD[m+1:1];
• an m+1 bit register arranged to separate upper m-bits ofthe received codeword from the insertion bit that was inserted during coding, via said encoder;
• a block inversion checker arranged to check for a bit inversion with respect to the upper m-bits of the received codeword, and produce a block control signal;
• a block inverter arranged to perform a selective block inversion with respect to the upper m-bits of the received codeword according to the block control signal;
• a bit manipulation checker arranged to check for a bit manipulation with respect to a block output from said block inverter, and produce a bit control signal for recovering to information data prior to coding;
• and
• a bit manipulator arranged to perform an inverse manipulation of coding with respect to the block output from the block inverter in response to the bit control signal to thereby recover the information data.