Differential logic circuit and method of use
AssigneeSemiconductor Components Industries, LLC
InventorIra Emmet Baskett
Life of this patent
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Abstract
A differential logic gate (36) is provided with three current sources (56, 58and 60). Current source (56) provides keep alive current flowing through transistor (48) when a logic low is presented at the base terminal of transistor 48. Current source (60) provides keep alive current flowing through transistor (50) when a logic low is presented at the base terminal of transistor 50. Current source (58) provides additional current drive when either transistor (48) or transistor (50) is conducting maximum current. Keep alive current sources (56 and 60) allow operation of differential logic gate (36) at reduced peak to peak voltage transitions with reduced ringing and smoother logic transitions.
Claims20
A logic gate, comprising:
- an amplifier coupled to receive an input signal and coupled to provide an amplified signal at a first node in response to the input signal;
- a first current source coupled to receive a first portion of the amplified signal at the first node, wherein the first portion is a constant signal maintaining the amplifier in a minimally conductive state;
- and
- a second current source coupled to receive a second portion of the amplified signal at a second node, wherein the amplified signal consists entirely of the first and second portions.
A differential logic gate, comprising:
- a differential amplifier coupled to receive first and second input signals and coupled to provide first and second output signals;
- a first current source coupled to receive a first portion of the first output signal;
- a second current source coupled to receive a first portion of the second output signal;
- and
- a third current source coupled to receive a second portion of first and second output signals.
A method of operating a differential logic gate operating between minimum and maximum conduction states in response to first and second input states, comprising:
- generating a first amplifier output signal in response to the first input state to maintain the amplifier in the minimum conduction state;
- and
- generating a second amplifier output signal in response to the second input state to increase the conduction state of the amplifier to the maximum conduction state, wherein the amplifier consists of a single transistor conducting the entire first and second amplifier output signals.
A method of operating a differential logic gate, comprising:
- supplying a source of constant current to an input amplifier;
- maintaining a constant operational state of the input amplifier with the source of constant current while receiving first and second input states;
- and
- controlling a level of gain of the input amplifier to a substantially constant value by maintaining the constant operational state independent of the first and second input states, wherein the input amplifier conducts the entire source of constant current during first and second input states.
An integrated circuit comprising a differential logic gate coupled for receiving an input signal and providing an output signal to a utilization circuit, the differential logic gate comprising:
- a differential amplifier coupled to receive first and second input signals and coupled to provide first and second output signals;
- a first current source coupled to receive a first portion of the first output signal;
- a second current source coupled to receive a first portion of the second output signal;
- and
- a third current source coupled to receive a second portion of first and second output signals.
A circuit, comprising:
- an emitter-coupled transistor pair having first and second control terminals coupled to receive first and second input signals;
- a first current source coupled to common emitters of the emitter-coupled transistor pair;
- and
- second and third standby current sources coupled to the common emitters of the emitter-coupled transistor pair.
Dependencies are inferred from the claim text.