High voltage tolerant interface circuit

A semiconductor memory device having an internal circuit, comprising:

• a pad at which a first signal is output and a second signal is input;
• an output buffer having a plurality of MOS transistors with first electrodes connected to the pad, the output buffer converts a first voltage level of data output from the internal circuit and provides the converted first voltage level to the pad for output as the first signal;
• an input buffer having at least one MOS transistor with a first electrode connected to the pad, the input buffer converts a second voltage level of the second signal input to the pad and transfers the converted second voltage level to the internal circuit;
• and
• a voltage control unit connected to the pad, that provides an internal power supply voltage to the MOS transistors of the output and input buffers,
• wherein the internal power supply voltage is equal to an external power supply voltage when the external power supply voltage is applied to the semiconductor memory device, and
• wherein the internal power supply voltage is equal to a predetermined voltage level when the external power supply voltage is not applied to the semiconductor memory device and a high-voltage of magnitude greater than the external power supply voltage is input to the pad.