Latch type level shift circuit

A latch type level shift circuit comprising:

• an internal power supply potential generating circuit generating first and second internal power supply potentials;
• a latch circuit having first and second nodes and driven by the first and second internal power supply potentials;
• a level shifter having first and second output terminals and driven by the first internal power supply potential and a fixed potential;
• a first MOS transistor having a gate connected to the first output terminal and having a function of supplying the first internal power supply potential to the first node when said first MOS transistor is set into the ON state;
• and
• a second MOS transistor having a gate connected to the second output terminal and having a function of supplying the first internal power supply potential to the second node when said second MOS transistor is set into the ON state.

A latch type level shift circuit in which first and second power supply potentials supplied from an exterior of a chip to an interior thereof and third and fourth power supply potentials generated in the chip are used, comprising:

• a latch circuit having first and second nodes, outputting one of the third power supply potential as a high level and the fourth power supply potential as a low level to the first node, and outputting the other one of the third power supply potential as the high level and the fourth power supply potential as the low level to the second node;
• a logic circuit outputting the first power supply potential as a high logic level and outputting the second power supply potential as a low logic level;
• a level shifter having first and second output terminals, converting the first power supply potential output from said logic circuit to the third power supply potential, outputting one of the third power supply potential as a high output level and the second power supply potential as a low output level to the first output terminal, and outputting the other one of the third power supply potential as the high output level and the second power supply potential as the low output level to the second output terminal;
• a first MOS transistor connected between the first node and the first output terminal;
• a second MOS transistor connected between the second node and the second output terminal;
• and
• an internal power supply potential generating circuit generating the third and fourth power supply potentials and having a function of changing the values of the third and fourth power supply potentials;
• wherein a potential of a substrate in which both of said first and second MOS transistors are formed varies according to the values of the third and fourth power supply potentials.