Clock control method and circuit

A clock control method for reducing jitter, comprising the steps of:

• providing a timing averaging circuit which generates, and outputs from an output terminal, a signal having a time difference obtained by internally dividing a time difference between first and second signals, which are input respectively from first and second input terminals, at a prescribed ratio;
• inputting first and second clock signals having a time difference between them to said timing averaging circuit;
• and
• generating a clock signal having a time difference obtained by internally dividing a time difference between pulses of the first and second clock signals to reduce jitter.

A clock control circuit, comprising:

• a plurality of serially connected timing averaging circuits each having two parallel-connected timing dividing circuits, said timing dividing circuits generating, and outputting from an output terminal, a signal which undergoes a transition after a delay equivalent to a time difference obtained by internally dividing a time difference between first and second signals, which are input respectively to first and second input terminals, wherein a transition timing of the first or second signal, whichever is earlier, is used as a reference,
• wherein first and second clock signals are input respectively to first and second input terminals of each of said timing dividing circuits and forms a first stage of said timing averaging circuits,
• wherein first and second output signals, which are output from output terminals of each of said timing dividing circuits of a timing averaging circuit of a preceding stage, are input respectively to first and second input terminals of each of said timing dividing circuits and forms a timing averaging circuit of a succeeding stage, and
• wherein first and second output signals from output terminals of each of the timing dividing circuits of a timing averaging circuit of a final stage are extracted.

A clock control circuit, comprising:

• at least one timing dividing circuit that generates a signal having a phase difference obtained by internally dividing a phase difference between a predetermined set of clock phases of multiphase clocks having mutually different phases, said timing dividing circuit being provided in a number equivalent to the number of clock phases;
• means for generating a signal having a duration equivalent to the phase difference between a predetermined pair of outputs regarding outputs of the plurality of timing dividing circuits;
• and
• means for generating a multiphase clock by combining two signals of a predetermined pair generated in a number equivalent to the number of clock phases.

A clock control circuit, comprising:

• a plurality of serially connected timing averaging circuits each having two parallel-connected timing dividing circuits that generate, and output from an output terminal, a signal which undergoes a transition after a delay equivalent to a time difference obtained by internally dividing a time difference between first and second signals, which are input respectively to first and second input terminals, wherein transition timing of the first or second signal, whichever is earlier, is used as a reference;
• frequency divider circuit that frequency divides an entered clock signal to first and second clock signals and outputs the first and second clock signals,
• wherein the first and second clock signals from said frequency divider circuit are input respectively to first and second input terminals of each of said parallel-connected timing dividing circuits that constitute a first stage of said timing averaging circuits,
• wherein first and second output signals, which are output from the output terminals of each of said timing dividing circuits of a timing averaging circuit of a preceding stage, are input respectively to first and second input terminals of each of said timing dividing circuits that constitute a timing averaging circuit of a succeeding stage;
• and
• a combining circuit, to which first and second output signals from the output terminal s of each of the timing dividing circuits of a timing averaging circuit of a final stage are input, said combining circuit outputting these signals upon multiplexing the same.