Timing controller and controlled delay circuit for controlling timing or delay time of a signal by changing phase thereof
AssigneeFujitsu Limited
InventorYoshinori Okajima
Life of this patent
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Abstract
A controlled delay circuit has a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which receives third signals generated in the first gate chain and representing the time difference, is used to provide an appropriate delay time from an input to an output depending on the time difference. The controlled delay circuit is capable of properly controlling the timing of the control signal according to the period of the control signal.
Claims88
A controlled delay circuit comprising:
- a first gate chain having gate circuits connected in series to transmit a signal in a first direction;
- a second gate chain having gate circuits connected in series to transmit a signal in a second direction opposite to said first direction;
- and
- a control circuit for activating and inactivating said first gate chain according to a first control signal and also for activating and inactivating said second gate chain according to a second control signal;
- and
- a data transfer circuit transferring data in the gate circuits in said first gate chain to the gate circuits in said second gate chain, and the data being output from said second gate chain in a manner opposite that of the data running through said first gate chain.
A controlled delay circuit as claimed in claim 4, wherein the first and second control signals are produced according to a common signal, which is set to a first level to activate said first gate chain and inactivate said second gate chain and to a second level to inactivate said first gate chain and activate said second gate chain.
A controlled delay circuit comprising:
- a first gate chain having a plurality of first delay units connected in series of a first direction, getting a first control signal to enable/disable a signal propagation through said first delay units, wherein an input signal during a first enabled period instructed by a first control signal being transferred to a number of digital signals output from said first delay units, and the input signal being digitalized by a unit time-interval, and output;
- and
- a second gate chain having a plurality of second delay units connected in series of a second direction opposite to said first direction, getting a second control signal to enable/disable signal propagation through said second delay units, wherein the digital signals being transferred as an output signal running through said second gate chain during a second enabled period instructed by a second control signal.
An electric circuit comprising a controlled delay circuit for changing a phase of an external first clock signal, to form a second clock signal, an optional circuit, and a buffer for providing an output according to an output of said optional circuit in synchronization with the second clock signal, wherein said controlled delay circuit comprises:
- a first gate chain having gate circuits connected in series to transmit a signal in a first direction;
- a second gate chain having gate circuits connected in series to transmit a signal in a second direction opposite to said first direction;
- and
- a control circuit for activating and inactivating said first gate chain according to a first control signal and also for activating and inactivating said second gate chain according to a second control signal;
- and
- a data transfer circuit transferring data in the gate circuits in said first gate chain to the gate circuits in the second gate chain, and the data being output from said second gate chain in a manner opposite that of the data running through said first gate chain.
An electric circuit comprising a controlled delay circuit for changing a phase of an external first clock signal, to form a second clock signal, an optional circuit, and a buffer for providing an output according to an output of said optional circuit in synchronization with the second clock signal, where said controlled delay circuit comprises:
- a first gate chain having a plurality of first delay units connected in series of a first direction, getting a first control signal to enable/disable signal propagation through said first delay units, wherein an input signal during a first enabled period instructed by a first control signal being transferred to a number of digital signals output from said first delay units, and the input signal being digitalized by a unit time-interval, and output;
- and
- a second gate chain having a plurality of second delay units connected in series of a second direction opposite to said first direction, getting a second control signal to enable/disable signal propagation through said second delay units, wherein the digital signals being transferred as an output signal running through said second gate chain during a second enabled period instructed by a second control signal.
An electric circuit as claimed in claim in 67, wherein each of gate circuits of said first and second gate chains is an inverter, a level of a voltage applied to said inverters being changed to activate one of said first and second gate chains.
Dependencies are inferred from the claim text.