System and method for phase alignment of a plurality of clock pulses when starting, stopping and pulsing clocks
AssigneeInternational Business Machines Corporation
InventorsMichael Stephen Floyd, Kevin F. Reick, Timothy Michael Skergan
Life of this patent
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Abstract
The present invention is embodied in a clock controller for generating and controlling the phase alignment of a plurality of ratioed sub-clocks. A master clock is preferably input to a clock splitter to provide a plurality of slave clocks. Phase holds, generated from the slave clocks, are then used to gate each of the slave clocks to produce ratioed clocks that produce phase aligned clock pulses at integer factors of the master clock frequency. The clock controller controls the ratioed clocks by processing commands to start, stop, or pulse the ratioed clocks.
Claims23
A method for aligning the phase of at least one clock signal to a master clock, comprising:
- waiting for alignment of at least one phase hold signal;
- combining at least one phase hold signal to at least one slave clock signal to generate at least one phase aligned sub-clock signal;
- and
- wherein waiting for the alignment of at least one phase hold signal comprises waiting until the count of a first looping counter is the same as the count of a second looping counter.
A method for aligning the phase of at least one clock signal to the phase of a master clock, comprising:
- splitting a master clock to generate at least one phase aligned sub-clock;
- generating at least one continuously running phase hold signal by decoding the count of a first counter;
- and
- masking each sub-clock with each of the phase hold signals to generate at least one phase aligned clock signal.
A system for phase alignment of at least one clock signal, comprising:
- a clock splitter for generating at least one continuously running slave clock signals from a first clock signal, wherein each of the at least one slave clock signals are phase aligned to the first clock signal;
- a first counter coupled to the clock splitter, wherein the count of the first counter is incremented for each clock pulse of one of the slave clock signals;
- a phase hold generator coupled to the first counter for decoding the count of the first counter and generating at least one continuously running phase hold signal;
- and
- a second clock for generating at least one phase aligned clock signal by combining each of the at least one slave clock signals with one of each of the at least one phase hold signals, and wherein each of the phase aligned clock signals are phase aligned to the first clock signal.
Dependencies are inferred from the claim text.