Back to results
US 6,333,646 B1Granted
Abnormal clock detector and abnormal clock detecting apparatus
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorTakayuki Tsuzuki
Life of this patent
Estimating the term…
Abstract
Frequencies of clocks CLK1 and CLK2 are divided in frequency divider circuits (11 to 14), frequency-divided clocks CLK1A and CLK1B are input into clock comparators (15) and (16). Frequency-divided clocks CLK2A and CLK2B are input into clock comparators (15) and (16). The clock comparator (15) counts the number of pulses of the clock CLK1A based on the clock CLK2B and outputs an error signal ERR1. The clock comparator (16) counts the number of pulses of the clock CLK2B based on the clock CLK1B and outputs an error signal ERR2. An abnormal clock is detected by examining states of the error signals ERR1 and ERR2.
Claims4
An abnormal clock detector which receives a first clock signal and a second clock signal and detects an abnormality in the frequency of any of the first clock signal or the second clock signal, said abnormal clock detector comprising:
- a first frequency divider circuit which divides the frequency of the first clock signal to output a first frequency division clock signal;
- a second frequency divider circuit which divides the frequency of the first clock signal to output a first reset signal;
- a third frequency divider circuit which divides the frequency of the second clock signal to output a second frequency division clock signal;
- a fourth frequency divider circuit which divides the frequency of the second clock signal to output a second reset signal;
- a first clock comparison circuit which receives the first frequency division clock signal and the second reset signal, counts the number of pulses of the first frequency division clock signal based on a state of the second reset signal, and outputs a first error signal indicative of abnormal clock when the counted number of pulses exceeds a predetermined value;
- and
- a second clock comparison circuit which receives the second frequency division clock signal and the first reset signal, counts the number of pulses of the second frequency division clock signal based on a state of the first reset signal, and outputs a second error signal indicative of abnormal clock when the counted number of pulses exceeds a predetermined value, wherein
- each of said first clock comparison circuit and said second clock comparison circuit comprises,
- an inverter gate inverting a state of the first reset signal or the second reset signal;
- a first shift resister comprising at least two stage flip-flops which receives the first frequency division clock signal or the second frequency division clock signal as a clock input, receives the first reset signal or the second reset signal as a reset input, and outputs a first output signal;
- a second shift register which receives the first frequency division clock signal or the second frequency division clock signal as a clock input, receives the first reset signal or the second reset signal inverted by said inverter gate as a reset input, and outputs a second output signal;
- and
- an OR gate for carrying out logical OR calculation of the first output signal and the second output signal to output the first error signal or the second error signal.
10 more elements
An abnormal clock detecting apparatus, comprising:
- at least three clock signals;
- a plurality of abnormal clock detectors in a number sufficient to enable comparison of said at least three clock signals;
- an abnormal clock judging circuit which outputs clock judging signals corresponding to said at least three clock signals, indicative of abnormal clock, based on an error signal output from said abnormal clock detectors;
- wherein each of said abnormal clock detectors receive a first clock signal and a second clock signal and detects an abnormality in the frequency of either of the first clock signal or the second clock signal, each abnormal clock detector comprising:
- a first frequency divider circuit which divides the frequency of the first clock signal to output a fist frequency division clock signal;
- a second frequency divider circuit which divides the frequency of the first clock signal to output a first reset signal;
- a third frequency divider circuit which divides the frequency of the second clock signal to output a second frequency division clock signal;
- a fourth frequency divider circuit which divides the frequency of the second clock signal to output a second reset signal;
- a first clock comparison circuit which receives the first frequency division clock signal and the second reset signal, counts the number of pulses of the first frequency division clock signal based on a state of the second reset signal, and outputs a first error signal indicative of abnormal clock when the counted number of pulses exceeds a predetermined value;
- and
- a second clock comparison circuit which receives the second frequency division clock signal and the first reset signal, counts the number of pulses of the second frequency division clock signal based on a state of the first reset signal, and outputs a second error signal indicative of abnormal clock when the counted number of pulses exceeds a predetermined value, wherein
- each of said first clock comparison circuit and said second clock comparison circuit comprises,
- an inverter gate inverting a state of the fist reset signal or the second reset signal;
- a first shift register comprising at least two stage flip-flops which receives the first frequency division clock signal or the second frequency division clock signal as a clock input, receives the first reset signal or the second reset signal as a reset input, and outputs a first output signal;
- a second shift register which receives the first frequency division clock signal or the second frequency division clock signal as a clock input, receives the first reset signal or the second reset signal inverted by said inverter gate as a reset input, and outputs a second output signal;
- and
- an OR gate for carrying out logical OR calculation of the first output signal and the second output signal to output the first error signal or the second error signal.
14 more elements
Dependencies are inferred from the claim text.