Process and structure for an interlock and high performance multilevel structures for chip interconnects and packaging technologies
AssigneeInternational Business Machines Corporation
InventorCyprian Emeka Uzoh
Life of this patent
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Abstract
Method and structures for making a highly reliable metal interlock structure with continuous via and line structures. The absence of barrier layers between vias and lines or absence of interlevel dielectric layer is used to enhance chip performance.
Claims11
A plated structure obtained by a process which comprises providing a substrate having vias therein;
- depositing a metallic conductive seed layer in the vias and lines with undercuts;
- and filling the vias by electroplating copper by providing an acidic electrolytic copper bath containing an aliphatic alkoxylate surface active agent in an amount sufficient to suppress etching of the seed layer;
- providing an electrode;
- and passing an electric current through the plating bath in a direction to make the substrate a cathode.
A multilevel interconnect damascene structure which comprises a mechanical interlocked copper or copper alloy conductive feature, and which does not contain a barrier layer between metal levels.
A multilevel interconnect dual damascene structure which comprises a mechanical interlocked copper or copper alloy conductive feature, and which does not contain a barrier layer between metal levels.
A multilevel interconnect structure which comprises a mechanical interlocked copper or copper alloy conductive feature, and which does not contain a barrier layer between metal levels and does not contain an interlevel dielectric layer.
Dependencies are inferred from the claim text.