Wafer thickness compensation for interchip planarity

An integrated circuit package, comprising:

• a carrier having a topography of mesas projected from a surface, said mesas having inwardly sloping sides;
• and
• individual semiconductor circuit chips, each said semiconductor circuit chip having a device side surface and an opposite bottom surface, said opposite bottom surface having a topography of a recess conversely matching a respective one of said mesas of said carrier to permit self-aligned positioning of each said semiconductor circuit chip on said carrier,
• wherein said individual semiconductor circuit chips have variations in a chip thickness, each said semiconductor circuit chip having said chip thickness less than or equal to a reference thickness, the difference between said chip thickness and said reference thickness being a thickness offset, and
• wherein a width of said recess in said opposite bottom surface of each said semiconductor circuit chip is controlled so that for each said individual semiconductor circuit chip, alignment of said recess on the respective one of said mesas of said carrier elevates said opposite bottom surface above said carrier surface by an amount equal to said respective thickness offset, thereby placing said device side surface of said semiconductor circuit chip in the same plane.