Patterned SOI regions in semiconductor chips

A semiconductor structure comprising:

• a semiconductor substrate containing silicon having an upper surface,
• said substrate having at least one silicon-on-insulator region and at least one bulk semiconductor region adjacent said silicon-on-insulator region, wherein said silicon-on-insulator region includes a buried oxide region having continuous oxide from a first to a second side of said buried oxide region along a path generally parallel to a major surface of said substrate,
• wherein said silicon-on-insulator region contains CMOS logic circuitry and said bulk semiconductor region contains DRAM circuitry including a plurality of trench capacitors.

A semiconductor structure comprising:

• a semiconductor substrate containing silicon having an upper surface,
• said substrate having at least one silicon-on-insulator region and at least one bulk semiconductor region adjacent said silicon-on-insulator region, wherein said silicon-on-insulator region includes a buried oxide region having continuous oxide from a first to a second side of said buried oxide region along a path generally parallel to a major surface of said substrate,
• wherein said silicon-on-insulator region contains a plurality of FET's and said bulk semiconductor region contains a plurality of trench capacitors.

A semiconductor structure comprising:

• a semiconductor substrate containing silicon having an upper surface,
• said substrate having at least one silicon-on-insulator region and at least one bulk semiconductor region adjacent said silicon-on-insulator region, wherein said silicon-on-insulator region includes a buried oxide region having continuous oxide from a first to a second side of said buried oxide region along a path generally parallel to a major surface of said substrate,
• wherein said silicon-on-insulator region includes a buried oxide region having a first portion having an upper surface at said upper surface of said semiconductor substrate and a second portion with an upper surface at a first depth with respect to said upper surface of said semiconductor substrate to provide a silicon containing layer above said second portion having a first thickness.

A semiconductor structure comprising:

• a semiconductor substrate containing silicon having an upper surface,
• said substrate having at least one silicon-on-insulator region and at least one bulk semiconductor region adjacent said silicon-on-insulator region, wherein said silicon-on-insulator region includes a buried oxide region having continuous oxide from a first to a second side of said buried oxide region along a path generally parallel to a major surface of said substrate,
• further including a trench formed in said semiconductor substrate at the edge of said silicon-on-insulator region.

A semiconductor structure comprising:

• a semiconductor substrate containing silicon having an upper surface,
• said substrate having at least one silicon-on-insulator region and at least one bulk semiconductor region adjacent said silicon-on-insulator region, wherein said silicon-on-insulator region contains CMOS logic circuitry and said bulk semiconductor region contains DRAM circuitry,
• further including a trench formed at the edge of said silicon-on-insulator region to intersect and remove crystalline defects.

A semiconductor structure comprising:

• a semiconductor substrate containing silicon having an upper surface,
• said substrate having at least one silicon-on-insulator region and at least one bulk semiconductor region adjacent said silicon-on-insulator region, wherein said silicon-on-insulator region contains CMOS logic circuitry and said bulk semiconductor region contains DRAM circuitry,
• further including a trench formed at the edge of said bulk semiconductor region to intersect and remove bulk semiconductor region crystalline defects.

A semiconductor structure comprising:

• a semiconductor substrate containing silicon having an upper surface,
• said substrate having at least one silicon-on-insulator region and at least one bulk semiconductor region adjacent said silicon-on-insulator region, wherein said silicon-on-insulator region includes a buried oxide region having continuous oxide from a first to a second side of said buried oxide region along a path generally parallel to a major surface of said substrate,
• further including a trench formed through said silicon-on-insulator region.

A structure for forming electrical devices therein comprising:

• a single crystal semiconductor substrate containing silicon having an upper surface, and
• a plurality of spaced apart silicon-on-insulator regions in said substrate having predetermined horizontal dimensions to provide a single crystal layer respectively over buried oxide regions, each said buried oxide region having continuous oxide from a first to a second side of said respective buried oxide region along a path generally parallel to a major surface of said substrate,
• wherein first and second portions of one of said buried oxide regions are at first and second respective depths below said upper surface to provide a single crystal silicon containing layer having respective first and second thickness.

A structure for forming electrical devices therein comprising:

• a single crystal semiconductor substrate containing silicon having an upper surface, and
• a plurality of spaced apart silicon-on-insulator regions in said substrate having predetermined horizontal dimensions to provide a single crystal layer respectively over buried oxide regions, each said buried oxide region having continuous oxide from a first to a second side of said respective buried oxide region along a path generally parallel to a major surface of said substrate,
• wherein said buried oxide regions contain material selected from the group consisting of silicon precipitates and silicon islands.

A structure for forming electrical devices therein comprising:

• a single crystal semiconductor substrate containing Si having an upper surface, and
• a plurality of buried oxide regions formed therein by ion implantation of oxygen therein through openings in a patterned mask to provide a single crystal layer respectively over said buried oxide regions,
• wherein portions of one of said buried oxide regions are at respective depths below said upper surface to provide a single crystal layer thereover having a plurality of thickness.

A structure for forming electrical devices therein comprising:

• a single crystal semiconductor substrate containing Si having an upper surface, and
• a plurality of buried oxide regions formed therein by ion implantation of oxygen therein through openings in a patterned mask to provide a single crystal layer respectively over said buried oxide regions,
• wherein two of said buried oxide regions are at first and second respective depths below said upper surface to provide a single crystal layer thereover having first and second thickness.