Semiconductor memory device having redundancy function
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorTakashi Itou
Life of this patent
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Abstract
The semiconductor memory device includes normal word lines, spare word lines and bit lines. Space between the spare word lines is made wider than the space between the normal word lines. Further, the space between the normal word line and the spare word line is also made wider. Thus possibility of contact defect caused by a foreign matter in the steps of manufacturing can be reduced. Further, the size of the storage node of a spare memory cell is made larger than that of the storage node of a normal memory cell. Thus capacitance of the spare memory cell can be increased. Thus possibility of defects in spare memory cells is reduced ensuring repairment.
Claims6
A semiconductor memory device, comprising:
- plurality of normal memory cells arranged in a matrix of rows and columns;
- a plurality of normal word lines provided corresponding to the rows of said plurality of normal memory cells;
- a plurality of spare memory cells arranged in a matrix of rows and columns for replacing a defective normal memory cell among said plurality of normal memory cells;
- and
- a plurality of spare word lines provided corresponding to the rows of said plurality of spare memory cells;
- wherein
- said plurality of spare word lines are arranged such that minimum space between said plurality of spare word lines is made wider than minimum space between said plurality of normal word lines.
Dependencies are inferred from the claim text.