US 6,333,254 B1 · Methods of forming a local interconnect method of fabricating integrated circuitry comprising an SRAM cell having a local interconnect and having circuitry peripheral to the SRAM cell and method of forming contact plugs

Abstract

In one implementation, a substrate is provided which has at least two nodes to be electrically connected. A first conductivity type semiconductive material is formed over and in electrical connection with one of the nodes. A conductive diffusion barrier material is formed over and in electrical connection with the first conductivity type semiconductive material. A second conductivity type semiconductive material is formed over and in electrical connection with the first conductivity type semiconductive material through the conductive diffusion barrier material, and over and in electrical connection with another of the nodes. The first conductivity type semiconductive material, the conductive diffusion barrier material and the second conductivity type semiconductive material are formed into a local interconnect electrically connecting the one node and the another node. Local interconnects fabricated by this and other methods are also contemplated. The invention includes in one implementation a method of forming contact plugs.

Claims35

Dependent claims

A method of forming a local interconnect comprising:

providing a substrate having a gate of a first transistor and a source/drain region of a second transistor;
forming a first conductivity type semiconductive material over and in electrical connection with the first transistor gate;
forming a conductive diffusion barrier material over and in electrical connection with the first conductivity type semiconductive material;
forming a second conductivity type semiconductive material over and in electrical connection with the first conductivity type semiconductive material through the conductive diffusion barrier material, and over and in electrical connection with the source/drain region;
and
forming the first conductivity type semiconductive material, the conductive diffusion barrier material and the second conductivity type semiconductive material into a local interconnect electrically connecting the first transistor gate with the source/drain region.

3 more elements

A method of fabricating integrated circuitry comprising an SRAM cell having a local interconnect and having circuitry peripheral to the SRAM cell, the method sequentially comprising:

providing a substrate having at least first, second and third nodes of an SRAM cell to be electrically connected, and having a plurality of peripheral circuitry first conductivity type nodes and a plurality of peripheral circuitry second conductivity type nodes, the first node being a source/drain region of the first conductivity type of a first transistor of the SRAM cell, the second node being a gate of a second transistor of the SRAM cell, the third node being a source/drain region of the second conductivity type of a third transistor of the SRAM cell;
providing an insulative layer over the substrate;
in a first common masking step, forming a first local interconnect opening into the insulative layer to the first and second nodes and forming first contact openings to the peripheral circuitry first conductivity type nodes, the first local interconnect opening comprising an outline which forms only a portion of a total outline of the local interconnect being fabricated;
forming first conductivity type semiconductive material within the first local interconnect opening in electrical connection with the first and second nodes and within the peripheral circuitry first contact openings in electrical connection with the peripheral circuitry first conductivity type nodes;
in a second common masking step, forming a second local interconnect opening into the insulative layer to the third node and forming second contact openings to the peripheral circuitry second conductivity type nodes, the second local interconnect opening overlapping with the first local interconnect opening, with the first and second local interconnect openings together defining the total outline of the local interconnect being fabricated;
forming a conductive diffusion barrier material over and in electrical connection with the first conductivity type semiconductive material received within the first local interconnect opening and within the peripheral circuitry first contact openings, and within the second local interconnect opening in electrical connection with the third node, and within the peripheral circuitry second contact openings in electrical connection with the peripheral circuitry second conductivity type nodes;
and
forming second conductivity type semiconductive material within the second local interconnect opening and within the peripheral circuitry first contact openings over and in electrical connection with the respective first conductivity type semiconductive material received therewithin through the conductive diffusion barrier material, and within the peripheral circuitry second contact openings over and in electrical connection with the respective peripheral circuitry second conductivity type nodes through the conductive diffusion barrier material;
and forming the first conductivity type semiconductive material, the second conductivity type semiconductive material and the conductive diffusion barrier material into a local interconnect electrically connecting the first, second and third nodes.

6 more elements

A method of fabricating integrated circuitry comprising an SRAM cell having a local interconnect and having circuitry peripheral to the SRAM cell, the method comprising:

providing a substrate having at least first, second and third nodes of an SRAM cell to be electrically connected, and having a plurality of peripheral circuitry first conductivity type nodes and a plurality of peripheral circuitry second conductivity type nodes, the first node being a source/drain region of the first conductivity type of a first transistor of the SRAM cell, the second node being a gate of a second transistor of the SRAM cell, the third node being a source/drain region of the second conductivity type of a third transistor of the SRAM cell;
providing an insulative layer over the substrate;
in a first common masking step, forming a first local interconnect opening into the insulative layer to the first and second nodes and forming first contact openings to the peripheral circuitry first conductivity type nodes, the first local interconnect opening comprising an outline which forms only a portion of a total outline of the local interconnect being fabricated;
forming first conductivity type semiconductive material within the first local interconnect opening in electrical connection with the first and second nodes and within the peripheral circuitry first contact openings in electrical connection with the peripheral circuitry first conductivity type nodes;
in a second common masking step, forming a second local interconnect opening into the insulative layer to the third node and forming second contact openings to the peripheral circuitry second conductivity type nodes, the second local interconnect opening overlapping with the first local interconnect opening, with the first and second local interconnect openings together defining the total outline of the local interconnect being fabricated;
forming a conductive diffusion barrier material over and in electrical connection with the first conductivity type semiconductive material received within the first local interconnect opening and within the peripheral circuitry first contact openings, and within the second local interconnect opening in electrical connection with the third node, and within the peripheral circuitry second contact openings in electrical connection with the peripheral circuitry second conductivity type nodes;
forming second conductivity type semiconductive material within the second local interconnect opening and within the peripheral circuitry first contact openings over and in electrical connection with the respective first conductivity type semiconductive material received therewithin through the conductive diffusion barrier material, and within the peripheral circuitry second contact openings over and in electrical connection with the respective peripheral circuitry second conductivity type nodes through the conductive diffusion barrier material;
and
comprising recessing the first conductivity type semiconductive material within the first local interconnect opening and within the peripheral circuitry contact openings prior to forming the conductive diffusion barrier material.

6 more elements

A method of fabricating integrated circuitry comprising an SRAM cell having a local interconnect and having circuitry peripheral to the SRAM cell, the method comprising:

providing a substrate having at least first, second and third nodes of an SRAM cell to be electrically connected, and having a plurality of peripheral circuitry first conductivity type nodes and a plurality of peripheral circuitry second conductivity type nodes, the first node being a source/drain region of the first conductivity type of a first transistor of the SRAM cell, the second node being a gate of a second transistor of the SRAM cell, the third node being a source/drain region of the second conductivity type of a third transistor of the SRAM cell;
providing an insulative layer over the substrate;
in a first common masking step, forming a first local interconnect opening into the insulative layer to the first and second nodes and forming first contact openings to the peripheral circuitry first conductivity type nodes, the first local interconnect opening comprising an outline which forms only a portion of a total outline of the local interconnect being fabricated;
forming first conductivity type semiconductive material within the first local interconnect opening in electrical connection with the first and second nodes and within the peripheral circuitry first contact openings in electrical connection with the peripheral circuitry first conductivity type nodes;
in a second common masking step, forming a second local interconnect opening into the insulative layer to the third node and forming second contact openings to the peripheral circuitry second conductivity type nodes, the second local interconnect opening overlapping with the first local interconnect opening, with the first and second local interconnect openings together defining the total outline of the local interconnect being fabricated;
forming a conductive diffusion barrier material over and in electrical connection with the first conductivity type semiconductive material received within the first local interconnect opening and within the peripheral circuitry first contact openings, and within the second local interconnect opening in electrical connection with the third node, and within the peripheral circuitry second contact openings in electrical connection with the peripheral circuitry second conductivity type nodes;
forming second conductivity type semiconductive material within the second local interconnect opening and within the peripheral circuitry first contact openings over and in electrical connection with the respective first conductivity type semiconductive material received therewithin through the conductive diffusion barrier material, and within the peripheral circuitry second contact openings over and in electrical connection with the respective peripheral circuitry second conductivity type nodes through the conductive diffusion barrier material;
and
comprising recess etching the first conductivity type semiconductive material within the first local interconnect opening and within the peripheral circuitry contact openings prior to forming the conductive diffusion barrier material.

6 more elements

Dependencies are inferred from the claim text.

Methods of forming a local interconnect method of fabricating integrated circuitry comprising an SRAM cell having a local interconnect and having circuitry peripheral to the SRAM cell and method of forming contact plugs

Life of this patent

Methods of forming a local interconnect method of fabricating integrated circuitry comprising an SRAM cell having a local interconnect and having circuitry peripheral to the SRAM cell and method of forming contact plugs

Life of this patent

Abstract

Claims35