Two-step MOSFET gate formation for high-density devices
AssigneeInternational Business Machines Corporation
InventorsKevin K. Chan, Erin C. Jones, Paul M. Solomon
Life of this patent
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Abstract
A method of manufacturing a metal-oxide-semiconductor field effect transistor MOSFET device gate includes patterning and etching the mesa of a gate material. A dielectric layer is formed on the mesa and is planarized using chemical mechanical polishing (CMP). The active gate dimension is patterned and etched to form source and drain wells that extend down to an active area on either side of the MOSFET gate. In one further embodiment, the wells are filled with metal and the metal is planarized. The MOSFET device, in one embodiment, includes source and drain wells equally spaced from the active gate.
Claims19
A method of manufacturing a metal-oxide-semiconductor field effect transistor (MOSFET) device gate, the gate material having a chemical mechanical polish stopping layer deposited thereon;
- said method comprising:
- patterning and etching a mesa of gate material larger in size than an active gate dimension;
- forming at least one dielectric layer on the mesa;
- planarizing the at least one dielectric layer to the polish stopping layer using chemical mechanical polishing;
- and
- patterning and etching the gate material to the active device gate dimension to form source and drain wells that extend to the active area on either side of the gate.
A method of manufacturing a metal-oxide-semiconductor field effect transistor (MOSFET) device gate, the gate having a starting substrate of a semiconductor wafer having gate material of a gate dielectric, gate conductor and a chemical mechanical polish stopping layer deposited thereon;
- said method comprising:
- patterning and etching a mesa of the gate material larger in size than an active gate dimension;
- forming at least one dielectric layer on the mesa of the gate material;
- planarizing the at least one dielectric layer to the polish stopping layer using chemical mechanical polishing;
- and
- patterning and etching the gate material to the active device gate dimension to form source and drain wells that extend to the active area on either side of the MOSFET gate.
A method of manufacturing a metal-oxide-semiconductor field effect transistor (MOSFET) device gate, the gate having a topgate dimension, an active device gate dimension, said method comprising:
- supplying a semiconductor wafer having gate material of a dielectric, gate conductor and chemical mechanical polish stopping layers deposited thereon;
- patterning and etching a mesa of the gate material to a size larger than the active gate dimension;
- forming a dielectric layer on the mesa of the gate material;
- planarizing the dielectric layer to the polish stopping layer using chemical mechanical polishing;
- and
- patterning and etching the gate material to the active device gate dimension to form source and drain wells that extend to the active area on either side of the MOSFET gate.
Dependencies are inferred from the claim text.