Semiconductor device and manufacturing method thereof

A method of manufacturing a semiconductor device with a memory cell portion and a logic portion on a semiconductor substrate, having

• first MIS transistor formed in said memory cell portion,
• a second MIS transistor of a first conductivity type and a third MIS transistor of a second conductivity type formed in said logic portion,
• a gate electrode of said first MIS transistor, having a first polycrystalline silicon film and a first silicide layer,
• a gate electrode of said second MIS transistor, having a second polycrystalline silicon film and a second silicide layer,
• a gate electrode of said third MIS transistor, having a third polycrystalline silicon film and a second silicide layer, and
• source/drain active regions of said second MIS transistor and the third MIS transistor, having a third silicide layer,
• sheet resistance of the second silicide layer and sheet resistance of the third silicide layer being lower than sheet resistance of said first silicide layer, and
• a gate insulation film of said first MIS transistor being thicker than a gate insulation film of said second MIS transistor and a gate insulation film of the third MIS transistor, said method comprising the steps of:
• forming the gate insulation film of said second MIS transistor, the gate insulation film of the third MIS transistor, said second polycrystalline silicon film and the third polycrystalline silicon film, and forming patterns of the gate insulation film of said second MIS transistor and the gate insulation film of the third MIS transistor;
• forming sidewalls of said second MIS transistor and the third MIS transistor;
• forming the gate insulation film of said first MIS transistor, said first polycrystalline silicon film and the first silicide film, and forming a pattern of the gate electrode of said first MIS transistor;
• oxidizing a polycrystalline silicon residue produced in forming the pattern of the gate electrode of said first MIS transistor and a surface of said semiconductor substrate;
• forming an insulation film covering the gate electrode of said first MIS transistor;
• and
• turning the gate electrode of said second MIS transistor, the gate electrode and the source/drain active regions of the third MIS transistor into a silicide.

A method of manufacturing a semiconductor device with a memory cell portion and a logic portion on a semiconductor substrate, having

• a first MIS transistor formed on said memory cell portion,
• a second MIS transistor of a first conductivity type and a third MIS transistor of a second conductivity type formed in said logic portion,
• a gate electrode of said first MIS transistor, having a first polycrystalline silicon film and a first silicide layer,
• a gate electrode of said second MIS transistor, having a second polycrystalline silicon film and a second silicide layer, and
• a gate electrode of said third MIS transistor, having a third polycrystalline silicon film and a second silicide layer, and
• source/drain active regions of said second MIS transistor and the third MIS transistor, having a third silicide layer,
• sheet resistance of the second silicide layer and sheet resistance of the third silicide layer being lower than sheet resistance of said first silicide layer, and
• a gate insulation film of said first MIS transistor being thicker than a gate insulation film of said second MIS transistor and a gate insulation film of said third MIS transistor, said method comprising:
• forming the gate insulation film of said first MIS transistor and said first polycrystalline silicon film and a first silicide film, and forming a pattern of the gate electrode of said first MIS transistor;
• forming an insulation film covering the gate electrode of said first MIS transistor;
• forming the gate insulation film of said second MIS transistor, the gate insulation film of the third MIS transistor, the second polycrystalline silicon film and the third polycrystalline silicon film, and forming patterns of the gate electrode of said second MIS transistor and the gate electrode of the third MIS transistor;
• oxidizing a polycrystalline silicon residue produced in forming the patterns of the gate electrode of said second MIS transistor and the gate electrode of the third MIS transistor and a surface of said semiconductor substrate;
• forming sidewalls of said second MIS transistor and the third MIS transistor;
• and
• turning the gate electrode and the source/drain active regions of said second MIS transistor, and the gate electrode and the source/drain active regions of the third MIS transistor into a silicide.