System on chip (SOC) four-way switch crossbar system and method

A System On Chip (SOC) crossbar switching network with a small time delay comprising:

• N input nodes;
• N output nodes;
• n layers of N high impedance switches to multiplex signals between said input and output nodes;
• in which each switch has one signal input operatively connected to one corresponding input node, each said switch having 2i signal outputs, with each said switch selectively providing the input signal at one of said outputs, and in which each said switch has i control inputs to select which output is selected;
• and
• in which N=2(n+i+1), whereby each said output node is connectable to any said input node.

A System On Chip (SOC) crossbar connection network with a small time delay comprising:

• N functional input/output (I/O) nodes internal to the IC;
• M I/O pins to physically access the IC;
• (n−1) layers of N switches to multiplex signals between said input nodes and said switch layers;
• one final layer of M switches to multiplex signals from said final switch layer to said M physical pins;
• in which M is less than N;
• in which N=2(n+i+1);
• and
• in which each switch has 2i signal inputs operatively connected to said input nodes, each said switch multiplexing the input signals to provide an output signal at a signal output, and in which each said switch has i control inputs to select which input signal is output by said switch, whereby a plurality of said output nodes are connectable to a greater plurality of input nodes.

In a System On Chip (SOC), a method for crossbar networking input signals from N input nodes to N output nodes in n stages of decision making, where N=2(n+i+1), the method comprising the steps of:

• a) combining the N input signals into vectors of 2i bits each to form (N/2i) vectors;
• b) replicating each vector of Step a) a total of 2i times to form a total of N vectors;
• c) selecting one signal from each vector to provide an input signal to the next stage;
• d) cycling through Steps a)-c) a total of n times, whereby each output node is selectively connectable to each of the N input nodes through n steps of decision making.

In a System On Chip (SOC), a method for crossbar networking input signals from N functional I/Os in an IC to M external connector pins in n stages of decision making, where N=2(n+i+1), the method comprising the steps of:

• a) combining the N input signals into vectors of 2i bits each to form N/2i vectors;
• b) replicating each vector from Step a) a total of 2i times to form a total of N vectors;
• c) selecting one signal from each vector to provide an input signal to the next stage;
• d) cycling through Steps a)-c) a total of (n−1) times;
• e) combining the N input signals into vectors of 2i bit each to form N/2i vectors;
• f) replicating each vector form Step e) a total of at least (M/N)2i times to form a total of M vectors;
• and
• g) selecting one signal from each vector to provide an input signal to each of the M connector pins, whereby signals at the N functional I/Os are made available at the M connector pins.

In a System On Chip (SOC), a method for crossbar networking input signals from N functional I/Os in an IC to N external connector pins in n stages of decision making, where N=2(n+i+1), the method comprising the steps of:

• a) generating 2i signal paths for each of the N input signals;
• b) combining the (2i)N input signals into vectors of 2i bits to form N vectors;
• c) selecting one signal from each vector to provide an input signal to the next stage;
• and
• d) cycling through Steps a)-c) a total of n times, whereby each input node is selectively connectable to each of the N output nodes through n steps of decision making.