Charge-redistribution low-swing differential logic circuit
AssigneeIndustrial Technology Research Institute
InventorHong-Yi Huang
Life of this patent
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Abstract
A charge-redistribution low-swing differential logic circuit combining a differential logic network and a charge-redistribution circuit so as to provide a pair of complementary signals having only a small difference, thereby avoiding a time delay. Further, after a sense amplifier is used to amplify the signals, the resulting signals are outputted to sequential differential logic network, wherein the output swing can be reduced by a threshold voltage Vtn (Vtp) on a transistor. In addition, a pipeline is formed by the series connection structure controlled by a true-single-phase clock or by pseudo-single-phase clock, thereby achieving a designed circuit having high-speed and low power dissipation.
Claims15
A charge-redistribution low-swing differential logic circuit comprising:
- a charge-redistribution circuit including a first CMOS transistor and a second CMOS transistor, each coupled to a first potential terminal, wherein the gates of two CMOS transistors are coupled together to receive a clock pulse which is used to control the first and second CMOS transistors, thereby outputting a first complementary signal pair;
- a differential logic network having a first train of a plurality of nodes and a second train of a plurality of nodes, each train being respectively coupled between one of the first complementary signal pair and a second potential terminal, wherein one of the first complementary signal pair performs the charge-redistribution with one of the two trains of a plurality of nodes, and there is an input voltage difference between the first and second potential;
- a sense amplifier, coupled between the first and second potential, which is controlled by the clock pulse to sense and amplify the voltage difference of the first complementary signal pair, then to output a second complementary signal pair;
- and
- a precharge circuit, controlled by the clock pulse, and used by the sense amplifier before sensing for precharging terminals of the second complementary signal pair to a third potential with a value between the first and second potential.
A charge-redistribution low-swing differential logic circuit comprising:
- a charge-redistribution circuit, including a first transistor pair with a first common gate node connected to a clock, and a second transistor pair with a second common gate node connected to a complementary signal of the clock, wherein, the first transistor pair, coupled in series between a first potential and the second transistor pair, is controlled by the clock, and the second transistor pair is controlled by the complementary signal for outputting a first complementary signal pair;
- a differential logic network having a first train of a plurality of nodes and a second train of a plurality of nodes, each train being respectively coupled between one of the first complementary signal pair and a second potential, wherein one of the first complementary signal pair performs the charge-redistribution with one of the two trains, and there is a voltage difference between the first and second potential;
- a sense amplifier, coupled between the first and second potential, which is controlled by the clock to sense and amplify the voltage difference of the first complementary signal pair, then to output a second complementary signal pair;
- and
- a precharge circuit, controlled by the clock, and used by the sense amplifier before sensing for precharging terminals of the second complementary signal pair to a third potential that is between the first and second potential.
Dependencies are inferred from the claim text.