Formation of integrated circuit structure using one or more silicon layers for implantation and out-diffusion in formation of defect-free source/drain regions and also for subsequent formation of silicon nitride spacers

A process for forming an integrated circuit structure on a semiconductor substrate which comprises:

• a) forming a dopant-implant barrier layer containing nitrogen and silicon over a single crystal semiconductor substrate;
• b) forming a polysilicon gate electrode over said barrier layer;
• c) removing exposed portions of said barrier layer;
• d) forming a first amorphous silicon layer over said barrier layer and said polysilicon gate electrode;
• e) implanting said first amorphous silicon layer with a first dopant capable of forming doped regions in the underlying semiconductor substrate which are less heavily doped than source/drain regions subsequently formed in said substrate;
• f) annealing said first amorphous silicon layer:
• i) to form a first polysilicon layer;
• ii) to diffuse said implanted first dopant from said first silicon layer through said barrier layer into said substrate to form said doped regions in said substrate;
• and
• iii) to diffuse said implanted first dopant into said polysilicon gate electrode;
• g) then nitridating said first polysilicon layer, using a nitrogen plasma to convert said first polysilicon layer into a first silicon nitride layer;
• h) then anisotropically etching said first silicon nitride layer to form first silicon nitride spacers on the sidewalls of said polysilicon gate electrode;
• i) forming a second layer of amorphous silicon over said structure;
• j) implanting said second amorphous silicon layer with a second dopant capable of forming source/drain regions in the underlying semiconductor substrate;
• k) annealing said second amorphous silicon layer:
• i) to form a second polysilicon layer;
• and
• ii) to diffuse said implanted second dopant from said second silicon layer through said barrier layer into said substrate to form said source/drain regions in said substrate;
• l) then nitridating said second polysilicon layer, using a nitrogen plasma to convert said second polysilicon layer into a second silicon nitride layer;
• and
• m) then anisotropically etching said second silicon nitride layer to form second silicon nitride spacers adjacent said first silicon nitride spacers on the sidewalls of said polysilicon gate electrode;
• whereby source/drain regions are formed in said substrate separated from a channel region in said substrate beneath said gate electrode by less heavily doped regions in said substrate.

A process for forming an integrated circuit structure on a semiconductor substrate which comprises:

• a) forming a dopant-implant barrier layer containing nitrogen and silicon over a first area of a single crystal semiconductor substrate;
• b) forming a polysilicon gate electrode over a central portion of said barrier layer of smaller area than said first area;
• c) forming an amorphous silicon layer over said substrate, including said polysilicon gate electrode and exposed portions of said barrier layer;
• d) implanting said amorphous silicon layer with a first dopant at a first concentration capable of forming source/drain regions in the underlying single crystal semiconductor substrate;
• e) implanting said amorphous silicon layer with a second dopant having a faster diffusion rate than said first dopant, but at a second concentration smaller than said first concentration, and capable of forming doped regions in said substrate less heavily doped than said source/drain regions;
• f) annealing said amorphous silicon layer:
• i) to form a polysilicon layer;
• ii) to diffuse said implanted first and second dopants from said silicon layer into said substrate to form said source/drain regions and said less heavily doped regions in said substrate;
• and
• iii) to diffuse said dopants into said polysilicon gate electrode;
• whereby said faster diffusing second dopant will laterally diffuse toward a channel region in said substrate beneath said polysilicon gate electrode at a faster rate than said first dopant to thereby form said less heavily doped regions between said channel region and said source/drain regions;
• g) then nitridating said polysilicon layer, using a nitrogen plasma to convert said polysilicon layer into a silicon nitride layer;
• and
• h) then anisotropically etching said silicon nitride layer to form silicon nitride spacers on the sidewalls of said polysilicon gate electrode to electrically insulate said gate electrode from said source/drain regions in said substrate.

A process for forming an integrated circuit structure on a semiconductor substrate which comprises:

• a) forming a gate oxide layer over a single crystal semiconductor substrate;
• b) forming a silicon layer over said gate oxide layer;
• c) nitridating said silicon layer to form a dopant-implant barrier layer comprising a silicon and nitrogen compound over said gate oxide layer;
• d) forming a polysilicon gate electrode over said barrier layer;
• e) removing all of said barrier layer not under said polysilicon gate electrode;
• f) forming an amorphous silicon layer over exposed portions of said integrated circuit structure;
• g) implanting said amorphous silicon layer with a first dopant capable of forming doped regions in the underlying semiconductor substrate;
• h) annealing said amorphous silicon layer:
• 1) to crystallize said amorphous silicon layer into a polysilicon layer;
• 2) to diffuse said implanted first dopant from said silicon layer into said substrate to form said doped regions in said substrate;
• and
• 3) to diffuse said first dopant into said polysilicon gate electrode;
• i) then nitridating said polysilicon layer to convert said polysilicon layer into a first silicon nitride layer;
• and
• j) then anisotropically etching said silicon nitride layer to form first silicon nitride spacers on the sidewalls of said polysilicon gate electrode to electrically insulate said gate electrode from said doped regions in said substrate.

A process for forming an integrated circuit structure on a semiconductor substrate which comprises:

• a) forming a gate oxide layer of silicon oxide over a single crystal semiconductor substrate;
• b) nitridating said gate oxide layer to form a dopant-implant barrier layer comprising silicon, oxygen, and nitrogen over said single crystal semiconductor substrate;
• c) forming a polysilicon gate electrode over said barrier layer;
• d) removing all of said barrier layer not under said polysilicon gate electrode;
• e) forming an amorphous silicon layer over exposed portions of said integrated circuit structure;
• f) implanting said amorphous silicon layer with a first dopant capable of forming doped regions in the underlying semiconductor substrate;
• g) annealing said amorphous silicon layer:
• 1) to crystallize said amorphous silicon layer into a polysilicon layer;
• 2) to diffuse said implanted first dopant from said silicon layer into said substrate to form said doped regions in said substrate;
• and
• 3) to diffuse said first dopant into said polysilicon gate electrode;
• h) then nitridating said polysilicon layer to convert said polysilicon layer into a first silicon nitride layer;
• and
• i) then anisotropically etching said silicon nitride layer to form first silicon nitride spacers on the sidewalls of said polysilicon gate electrode to electrically insulate said gate electrode from said doped regions in said substrate.