Systems and methods for a disk controller memory architecture

A disk drive controller, comprising:

• a disk drive interface;
• a buffer memory coupled to at least receive data from said disk drive interface;
• a first processor;
• and
• a memory circuit loadable using direct memory access coupled to said buffer memory and said first processor, said memory circuit configured to operate as a first-in-first-out memory when transferring data between said buffer memory and said memory circuit during a first transfer via a first port, and said memory circuit configured to operate as a random access memory when being accessed by said first processor during a second transfer via a second port.

A mass storage device controller for interfacing a computer to a mass storage device, said mass storage device controller comprising:

• a mass storage buffer memory interface;
• a processor;
• and
• a first memory circuit loadable using a direct memory access transfer configured to be coupled to receive data from said mass storage buffer memory interface in a first-in-first-out manner using a first port, said memory circuit accessible by said processor as a random access memory using a second port.

A mass storage device controller for interfacing a mass storage device to a computer via an I/O bus, said mass storage device controller comprising:

• a buffer memory configured to receive data from said mass storage device and data from said I/O bus;
• a processor;
• and
• a memory circuit coupled to said buffer memory and said processor, said memory circuit configured to operate as a first-in-first-out memory during at least a first transfer of data between said memory circuit and said buffer memory, and said memory circuit configured to operate as a random access memory during at least a first transfer of data between said memory circuit and said processor.

A system for controlling a mass storage device, comprising:

• a host computer;
• a bus coupled to said host computer;
• a mass storage device;
• and
• a controller coupled to said bus and said mass storage device, said controller including:
• a first memory circuit configured to receive data from said mass storage device and data from said bus;
• a processor;
• and
• a second memory circuit coupled to said first memory circuit and said processor, said second memory circuit configured to operate as a first-in-first-out memory during at least a first transfer of data between said second memory circuit and said first memory circuit, and said second memory circuit configured to operate as a random access memory during at least a first transfer of data between said second memory circuit and said processor.

A mass storage device controller for interfacing a mass storage device to a computer via an I/O bus, said mass storage device controller comprising:

• a means for receiving data from said mass storage device and data from said I/O bus;
• a means for managing said mass storage device controller;
• and
• a means for storing data coupled to said means for receiving data and said means for managing, said means for storing data configured to operate as a first-in-first-out memory during at least a first transfer of data between said means for storing data and said means for receiving data, and said means for storing data configured to operate as a random access memory during at least a first transfer of data between said means for storing data and said means for managing data.

A method of transferring data between memories in a mass storage device controller, said method comprising the acts of:

• transferring a buffer length field associated with a data packet from a first memory to a first location of a second memory operable as a first-in-first-out (FIFO) memory, wherein at least a portion of the buffer length field includes information related to the amount of data being transferred via the data packet;
• transferring at least a portion of said data packet from said first memory to at least a second location of said second memory;
• and
• reading said buffer length field from said memory operable as a FIFO memory, and then reading said at least portion of said data packet from said second memory.

A method of accessing and storing data in a disk drive controller, comprising:

• receiving data in a buffer memory;
• transferring data from the buffer memory to a multiported memory located on the disk controller using a first port of the multiported memory, wherein the first port is a first-in-first-out port;
• transferring data between the multiported memory and a first disk controller processor using a second port of the multiported memory, wherein the first disk controller is configured to perform high-level tasks;
• and
• transferring data between the multiported memory and a second disk controller processor using a third memory port of the multiported memory, wherein the second disk controller processor is configured to perform low-level tasks.