Copper process compatible CMOS metal-insulator-metal capacitor structure and its process flow

A method of fabricating an integrated circuit on a substrate using damascene processing to form high performance, mixed-signal and high frequency Rf parallel plate capacitors, metal-insulator-metal (MIM) and Inductor devices, simultaneously, using copper metallurgy, for applications in CMOS circuits, the method comprising:

• providing a semiconductor single crystal silicon substrate or IC substrate module;
• providing a substrate having a layer of dielectric, silicon oxide;
• providing a first level conductor wiring surrounded by barrier material within the said layer of dielectric;
• depositing a metal protect buffer layer, silicon nitride, over said first level of conductor wiring;
• depositing an intermetal dielectric (IMD) layer over said metal protect buffer layer;
• patterning by coating, exposing and developing photoresist, forming a metal-insulator-metal capacitor, MIM/Inductor damascene openings, on said intermetal dielectric (IMD) layer, over select portions of said first level conductor wiring;
• etching and removing by reactive ion etching (RIE) the intermetal dielectric (IMD) in the exposed MIM/Inductor damascene openings, and etching through the exposed intermetal dielectric (IMD) stopping on the metal protect buffer layer;
• removing the patterning and masking material and removing the exposed metal protect buffer layer;
• depositing by chemical vapor deposition (CVD) an insulating protect buffer layer, silicon nitride, over the patterned intermetal dielectric (IMD) layer and over said first level of conductor wiring, that is exposed;
• depositing an MIM insulating layer over said insulating protect buffer layer;
• depositing a conducting metal buffer layer, silicon nitride, over said MIM insulating layer;
• patterning by coating, exposing and developing photoresist, to form dual damascene via/trench openings, or trench/via openings by a process reversal, on said intermetal dielectric (IMD), over select portions of said first level conductor wiring, while protecting the MIM/Inductor damascene openings, or areas, with unexposed photoresist;
• etching and removing by reactive ion etching (RIE) the exposed intermetal dielectric (IMD) in the intermetal dielectric (IMD) layer, forming dual damascene trench/via openings;
• stripping the remaining photoresist, thus forming in the intermetal dielectric (IMD) layer, open areas or openings for both dual damascene trench/via and MIM/Inductor;
• depositing thick conducting copper metal, by electrochemical deposition (ECD), over and in the intermetal dielectric (IMD), simultaneously filling all open areas or openings, for both dual damascene trench/via and MIM/Inductor;
• polishing off both excess conducting metal and excess conducting metal protect buffer layer by chemical mechanical polishing (CMP) and stopping on the insulating protect buffer layer to form simultaneously, by damascene processing, inlaid metal structures consisting of contact vias, metal interconnect lines, and MIM/Inductors.