US 6,327,693 B1 · Interconnect delay driven placement and routing of an integrated circuit design

Abstract

An EDA tool is provided with a placement and routing (P&R) module that optimizes placement and routing of an IC design in an interconnect delay driven manner. The P&R module systematically determines if it can improve (i.e. reduce) interconnect delay of the current critical interconnect routing path by determining if it can improve the interconnect delays of its constituting segments, each interconnecting two pins through a component. For each segment, the P&R module determines if the interconnect delay can be achieved by using different interconnect routing path interconnecting the two pins through the component replaced at a different location, and alternatively, through a logically equivalent component disposed at a different location.

Claims30

Dependent claims

A computer implemented method for optimizing placement and routing of an integrated circuit design comprising:

designating a group of critical interconnect routing paths from a plurality of interconnect routing paths in a given region;
and
automatically determining, for each of the designated critical interconnect routing paths, if interconnect delay of a path segment connecting a first pin to a second pin through a component can be reduced by any of a plurality of different paths, said plurality of different paths interconnecting the first pin to the second pin through the component re-placed at a different location, through a logically equivalent component, and through a logically equivalent component placed at a different location;
and
selecting, for each of the designated critical interconnect routing paths, one of the plurality of different paths to interconnect the first pin to the second pin based primarily on an amount of interconnect delay reduction achieved.

2 more elements

An article of manufacture comprising:

a recordable medium having recorded thereon a plurality of programming instructions for use to program a computer system to enable the computer system to be able to optimize placement and routing of an integrated circuit design, including
designating a group of critical interconnect routing paths from a plurality of interconnect routing paths in a given region;
and
automatically determining, for each of the designated critical interconnect routing paths, if interconnect delay of a path segment connecting a first pin to a second pin through a component can be reduced by any of a plurality of different paths, said plurality of different paths interconnecting the first pin to the second pin through the component re-placed at a different location, through a logically equivalent component, and through the logically equivalent component placed at a different location;
and
selecting, for each of the designated critical interconnect routing paths, one of the plurality of different paths to interconnect the first pin to the second pin based primarily on an amount of interconnect delay reduction achieved.

3 more elements

A computer system comprising:

a storage medium having stored therein a plurality of programming instructions;
a processor coupled to the storage medium to execute the programming instructions to optimize placement and routing of an integrated circuit design, including
designating a group of critical interconnect routing paths from a plurality of interconnect routing paths in a given region;
and
automatically determining, for each of the designated critical interconnect routing paths, if interconnect delay of a path segment connecting a first pin to a second pin through a component can be reduced by any of a plurality of different paths, said plurality of different paths interconnecting the first pin to the second pin through the component re-placed at a different location, through a logically equivalent component, and through the logically equivalent component placed at a different location;
and
selecting, for each of the designated critical interconnect routing paths, one of the plurality of different paths to interconnect the first pin to the second pin based primarily on an amount of interconnect delay reduction achieved.

4 more elements

Dependencies are inferred from the claim text.

Interconnect delay driven placement and routing of an integrated circuit design

Life of this patent

Interconnect delay driven placement and routing of an integrated circuit design

Life of this patent

Abstract

Claims30