Sense amplifier of semiconductor integrated circuit

A semiconductor integrated circuit comprising:

• a sense amplifier, wherein the sense amplifier amplifies an input signal received at a first input port and a complementary input signal received at a first complementary input port;
• a full differential amplifier, wherein the fall differential amplifier amplifies output of the sense amplifier, the full differential amplifier comprising:
• an input port, a complementary input port, an output port, and a complementary output port;
• a first differential amplifying unit, wherein the first differential amplifying unit increases a voltage at the output port when a voltage at the input port is larger than a voltage at the complementary input port, and reduces the voltage at the output port when the voltage at the input port is lower than the voltage at the complementary input port;
• a second differential amplifying unit, wherein the second differential amplifying unit reduces a voltage at the complementary output port when the voltage at the input port is larger than the voltage at the complementary input port, and increases the voltage at the complementary output port when the voltage at the input port is lower than the voltage at the complementary input port;
• and
• an output voltage level control circuit connected between the output port and the complementary output port, wherein the output voltage level control circuit controls the voltages at the output port and the complementary output port, the output voltage level control circuit comprising:
• an output voltage mean value sensing unit, wherein the mean value sensing unit senses a mean value of the voltages at the output port and at the complementary output port, the mean value sensing unit comprising a first resistor and a second resistor serially connected between the output port and the complementary output port, wherein the voltage mean value is output from a node between the first and second resistors;
• and
• an output mean value controller, wherein the mean value controller prevents the voltage mean value from increasing to more than a predetermined value, the mean value controller comprising a first NMOS transistor comprising a first source, a first gate, and a first drain, and a second NMOS transistor comprising a second source, a second gate, and a second drain, wherein the first and second gates are coupled to the node between the first and second resistors, the first drain is coupled to the output port, the second drain is coupled to the complementary output port, and the first source and the second source are coupled to a ground;
• and
• a latch, wherein the latch latches output of the full differential amplifier and outputs a latched output signal.

A full differential amplifier comprising:

• an input port, a complementary input port, an output port, and a complementary output port;
• a first differential amplifying unit, wherein the first differential amplifying unit increases a voltage at the output port when a voltage at the input port is larger than a voltage at the complementary input port, and reduces the voltage at the output port when the voltage at the input port is lower than the voltage at the complementary input port;
• a second differential amplifying unit, wherein the second differential amplifying unit reduces a voltage at the complementary output port when the voltage at the input port is larger than the voltage at the complementary input port, and increases the voltage at the complementary output port when the voltage at the input port is lower than the voltage at the complementary input port;
• and
• an output voltage level control circuit connected between the output port and the complementary output port, wherein the output voltage level control circuit controls the voltages at the output port and the complementary output port, the output voltage level control circuit comprising:
• an output voltage mean value sensing unit, wherein the mean value sensing unit senses a mean value of the voltages at the output port and at the complementary output port, the mean value sensing unit comprising a first resistor and a second resistor serially connected between the output port and the complementary output port, wherein the first and second resistors are approximately equal resistance, and wherein the voltage mean value is output from a node between the first and second resistors;
• and
• an output mean value controller, wherein the mean value controller prevents the voltage mean value from increasing to more than a predetermined value, the mean value controller comprising an NMOS transistor comprising a source, a drain, and a gate, wherein the gate is electrically coupled to the drain, the drain is electrically coupled to the node between the first and second resistors, and the source is electrically coupled to a ground.

A full differential amplifier comprising:

• an input port, a complementary input port, an output port, and a complementary output port;
• a first differential amplifying unit, wherein the first differential amplifying unit increases a voltage at the output port when a voltage at the input port is larger than a voltage at the complementary input port, and reduces the voltage at the output port when the voltage at the input port is lower than the voltage at the complementary input port;
• a second differential amplifying unit, wherein the second differential amplifying unit reduces a voltage at the complementary output port when the voltage at the input port is larger than the voltage at the complementary input port, and increases the voltage at the complementary output port when the voltage at the input port is lower than the voltage at the complementary input port;
• and
• an output voltage level control circuit connected between the output port and the complementary output port, wherein the output voltage level control circuit controls the voltages at the output port and the complementary output port, the output voltage level control circuit comprising:
• an output voltage mean value sensing unit, wherein the mean value sensing unit senses a mean value of the voltages at the output port and at the complementary output port, the mean value sensing unit comprising a first resistor and a second resistor serially connected between the output port and the complementary output port, wherein the voltage mean value is output from a node between the first and second resistors;
• and
• an output mean value controller, wherein the mean value controller prevents the voltage mean value from increasing to more than a predetermined value, the mean value controller comprising a first NMOS transistor comprising a first source, a first gate, and a first drain, and a second NMOS transistor comprising a second source, a second gate, and a second drain, wherein the first and second gates are coupled to the node between the first and second resistors, the first drain is coupled to the output port, the second drain is coupled to the complementary output port, and the first source and the second source are coupled to a ground.